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I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/55150
to look at the new patch set (#3).
Change subject: soc/intel/alderlake: enable ACPI S0ix DSM for Intel PEP ......................................................................
soc/intel/alderlake: enable ACPI S0ix DSM for Intel PEP
This is to enable S0ix device specific method _DSM (UUID: 57a6512e-3979-4e9d-9708-ff13b2508972) for Intel Power Engine Plug-in.
Alone with this change, one coreboot and two kernel changes are also required: https://review.coreboot.org/c/coreboot/+/55127 https://chromium-review.googlesource.com/2800280 https://chromium-review.googlesource.com/2800281
Once done, substate_requirement_registers is created under /sys/kernel/debug/pmc_core/ Use: 'cat /sys/kernel/debug/pmc_core/substate_requirement_registers' to check the content.
BUG=b:185437326 brya: _DSM method needs to implemented in coreboot for PMC requirement register.
Signed-off-by: Cliff Huang cliff.huang@intel.com Change-Id: I127c695eed9e2842996381c7559695f289cf4585 --- M src/soc/intel/alderlake/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/55150/3
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Cliff Huang (Code Review)