Change in coreboot[master]: soc/intel/tigerlake: configure ethernet fsp param

[Wonkyu Kim (Code Review)]

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39153 )

Change subject: soc/intel/tigerlake: configure ethernet fsp param
......................................................................

soc/intel/tigerlake: configure ethernet fsp param

Configure ethernet based on board config

BUG=none
BRANCH=none
TEST= build TGLRVP and check ethernet is disabled based on devicetree

Signed-off-by: Wonkyu Kim 
Change-Id: I3286f5fefc962a5e55b5554982271ed6b885f7d8
---
M src/soc/intel/tigerlake/fsp_params_tgl.c
1 file changed, 7 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/39153/1

diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c
index d22cde0..b8a7d91 100644
--- a/src/soc/intel/tigerlake/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/fsp_params_tgl.c
@@ -135,6 +135,13 @@
    		sizeof(params->SataPortsDevSlp));
    }

+	/* Lan */
+	dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 6);
+	if (!dev)
+		params->PchLanEnable = 0;
+	else
+		params->PchLanEnable = dev->enabled;
+
    /* Legacy 8254 timer support */
    params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER;
    params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER;

Change in coreboot[master]: soc/intel/tigerlake: configure ethernet

[Wonkyu Kim (Code Review)]

Hello Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39153

to look at the new patch set (#2).

Change subject: soc/intel/tigerlake: configure ethernet
......................................................................

soc/intel/tigerlake: configure ethernet

Configure ethernet based on board config

BUG=none
BRANCH=none
TEST= build TGLRVP and check ethernet is disabled based on devicetree

Signed-off-by: Wonkyu Kim 
Change-Id: I3286f5fefc962a5e55b5554982271ed6b885f7d8
---
M src/soc/intel/tigerlake/fsp_params_tgl.c
1 file changed, 7 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/39153/2

Change in coreboot[master]: soc/intel/tigerlake: configure ethernet

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39153 )

Change subject: soc/intel/tigerlake: configure ethernet
......................................................................

Patch Set 2: Code-Review+1

Change in coreboot[master]: soc/intel/tigerlake: configure ethernet

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39153 )

Change subject: soc/intel/tigerlake: configure ethernet
......................................................................

Patch Set 2:

(2 comments)

https://review.coreboot.org/c/coreboot/+/39153/2/src/soc/intel/tigerlake/fsp... 
File src/soc/intel/tigerlake/fsp_params_tgl.c:

https://review.coreboot.org/c/coreboot/+/39153/2/src/soc/intel/tigerlake/fsp... 
PS2, Line 138: Lan
LAN

https://review.coreboot.org/c/coreboot/+/39153/2/src/soc/intel/tigerlake/fsp... 
PS2, Line 143: 		params->PchLanEnable = dev->enabled;
Ternary operator?

Change in coreboot[master]: soc/intel/tigerlake: configure ethernet

[Wonkyu Kim (Code Review)]

Hello Shaunak Saha, build bot (Jenkins), Furquan Shaikh, Maulik V Vaghela, Subrata Banik, Nick Vaccaro, Aamir Bohra, Srinidhi N Kaushik, Raj Astekar, Patrick Rudolph, Venkata Krishna Nimmagadda,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39153

to look at the new patch set (#3).

Change subject: soc/intel/tigerlake: configure ethernet
......................................................................

soc/intel/tigerlake: configure ethernet

Configure ethernet based on board config

BUG=none
BRANCH=none
TEST= build TGLRVP and check ethernet is disabled based on devicetree

Signed-off-by: Wonkyu Kim 
Change-Id: I3286f5fefc962a5e55b5554982271ed6b885f7d8
---
M src/soc/intel/tigerlake/fsp_params_tgl.c
1 file changed, 7 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/39153/3

Change in coreboot[master]: soc/intel/tigerlake: configure ethernet

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39153 )

Change subject: soc/intel/tigerlake: configure ethernet
......................................................................

Patch Set 3: Code-Review+1

(2 comments)

https://review.coreboot.org/c/coreboot/+/39153/2/src/soc/intel/tigerlake/fsp... 
File src/soc/intel/tigerlake/fsp_params_tgl.c:

https://review.coreboot.org/c/coreboot/+/39153/2/src/soc/intel/tigerlake/fsp... 
PS2, Line 138: Lan
> LAN

Ack

https://review.coreboot.org/c/coreboot/+/39153/2/src/soc/intel/tigerlake/fsp... 
PS2, Line 143: 		params->PchLanEnable = dev->enabled;
> Ternary operator?

pchLanEnable is based on device enable in devicetree.
if condition is error case when PCI dev is not defined and it's for non TGL soc case.

Change in coreboot[master]: soc/intel/tigerlake: configure ethernet

[Srinidhi N Kaushik (Code Review)]

Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39153 )

Change subject: soc/intel/tigerlake: configure ethernet
......................................................................

Patch Set 3: Code-Review+2

Change in coreboot[master]: soc/intel/tigerlake: configure ethernet

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39153 )

Change subject: soc/intel/tigerlake: configure ethernet
......................................................................

Patch Set 3: Code-Review+2

Change in coreboot[master]: soc/intel/tigerlake: configure ethernet

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39153 )

Change subject: soc/intel/tigerlake: configure ethernet
......................................................................

soc/intel/tigerlake: configure ethernet

Configure ethernet based on board config

BUG=none
BRANCH=none
TEST= build TGLRVP and check ethernet is disabled based on devicetree

Signed-off-by: Wonkyu Kim 
Change-Id: I3286f5fefc962a5e55b5554982271ed6b885f7d8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39153
Reviewed-by: Srinidhi N Kaushik 
Reviewed-by: Subrata Banik 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/tigerlake/fsp_params_tgl.c
1 file changed, 7 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Subrata Banik: Looks good to me, approved
  Srinidhi N Kaushik: Looks good to me, approved
  Wonkyu Kim: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c
index d22cde0..fbc9f23 100644
--- a/src/soc/intel/tigerlake/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/fsp_params_tgl.c
@@ -135,6 +135,13 @@
    		sizeof(params->SataPortsDevSlp));
    }

+	/* LAN */
+	dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 6);
+	if (!dev)
+		params->PchLanEnable = 0;
+	else
+		params->PchLanEnable = dev->enabled;
+
    /* Legacy 8254 timer support */
    params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER;
    params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER;