Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43673 )
Change subject: soc/intel/jasperlake: Fix PMC_GPE_DW mapping ......................................................................
soc/intel/jasperlake: Fix PMC_GPE_DW mapping
PMC_GPE_DW mapping was not configured correctly and hence coreboot skipped programming Tier 1 GPIOs resulting in failure of S3 wake from Trackpad.
TEST=System should wake from S3 via trackpad
Change-Id: I59ce3720e0ffeefb2c9440bb300689def80211ea Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com --- M src/soc/intel/jasperlake/gpio.c M src/soc/intel/jasperlake/include/soc/pmc.h 2 files changed, 11 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/43673/1
diff --git a/src/soc/intel/jasperlake/gpio.c b/src/soc/intel/jasperlake/gpio.c index 3b3b262..397d668 100644 --- a/src/soc/intel/jasperlake/gpio.c +++ b/src/soc/intel/jasperlake/gpio.c @@ -189,7 +189,8 @@ { PMC_GPD, GPP_GPD }, { PMC_GPP_C, GPP_C }, { PMC_GPP_E, GPP_E }, - { PMC_GPP_F, GPP_F } + { PMC_GPP_F, GPP_F }, + { PMC_GPP_G, GPP_G } };
*num = ARRAY_SIZE(routes); diff --git a/src/soc/intel/jasperlake/include/soc/pmc.h b/src/soc/intel/jasperlake/include/soc/pmc.h index 5954a31..9eaa812 100644 --- a/src/soc/intel/jasperlake/include/soc/pmc.h +++ b/src/soc/intel/jasperlake/include/soc/pmc.h @@ -102,16 +102,17 @@ #define GPE0_DWX_MASK 0xf #define GPE0_DW_SHIFT(x) (4*(x))
-#define PMC_GPP_A 0x0 +#define PMC_GPP_G 0x0 #define PMC_GPP_B 0x1 -#define PMC_GPP_F 0x2 -#define PMC_GPD 0x3 -#define PMC_GPP_R 0x4 -#define PMC_GPP_S 0x6 +#define PMC_GPP_A 0x2 +#define PMC_GPP_R 0x3 +#define PMC_GPP_S 0x4 +#define PMC_GPD 0x5 +#define PMC_GPP_H 0x6 #define PMC_GPP_D 0x7 -#define PMC_GPP_C 0x8 -#define PMC_GPP_H 0xA -#define PMC_GPP_E 0xF +#define PMC_GPP_F 0x8 +#define PMC_GPP_C 0xA +#define PMC_GPP_E 0xB
#define GBLRST_CAUSE0 0x1924 #define GBLRST_CAUSE0_THERMTRIP (1 << 5)
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43673 )
Change subject: soc/intel/jasperlake: Fix PMC_GPE_DW mapping ......................................................................
Patch Set 1: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/43673/1/src/soc/intel/jasperlake/gp... File src/soc/intel/jasperlake/gpio.c:
https://review.coreboot.org/c/coreboot/+/43673/1/src/soc/intel/jasperlake/gp... PS1, Line 193: PMC_GPP_G, GPP_G nit: can be ordered as per community map
Hello build bot (Jenkins), Maulik V Vaghela, Aamir Bohra, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43673
to look at the new patch set (#3).
Change subject: soc/intel/jasperlake: Fix PMC_GPE_DW mapping ......................................................................
soc/intel/jasperlake: Fix PMC_GPE_DW mapping
PMC_GPE_DW mapping was not configured correctly and hence coreboot skipped programming Tier 1 GPIOs resulting in failure of S3 wake from Trackpad.
TEST=System should wake from S3 via trackpad
Change-Id: I59ce3720e0ffeefb2c9440bb300689def80211ea Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com --- M src/soc/intel/jasperlake/gpio.c M src/soc/intel/jasperlake/include/soc/pmc.h 2 files changed, 12 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/43673/3
Hello build bot (Jenkins), Maulik V Vaghela, Aamir Bohra, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43673
to look at the new patch set (#4).
Change subject: soc/intel/jasperlake: Fix PMC_GPE_DW mapping ......................................................................
soc/intel/jasperlake: Fix PMC_GPE_DW mapping
PMC_GPE_DW mapping was not configured correctly and hence coreboot skipped programming Tier 1 GPIOs resulting in failure of S3 wake from Trackpad.
TEST=System should wake from S3 via trackpad
Change-Id: I59ce3720e0ffeefb2c9440bb300689def80211ea Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com --- M src/soc/intel/jasperlake/gpio.c M src/soc/intel/jasperlake/include/soc/pmc.h 2 files changed, 13 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/43673/4
Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43673 )
Change subject: soc/intel/jasperlake: Fix PMC_GPE_DW mapping ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43673/1/src/soc/intel/jasperlake/gp... File src/soc/intel/jasperlake/gpio.c:
https://review.coreboot.org/c/coreboot/+/43673/1/src/soc/intel/jasperlake/gp... PS1, Line 193: PMC_GPP_G, GPP_G
nit: can be ordered as per community map
Done
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43673 )
Change subject: soc/intel/jasperlake: Fix PMC_GPE_DW mapping ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43673/4/src/soc/intel/jasperlake/in... File src/soc/intel/jasperlake/include/soc/pmc.h:
https://review.coreboot.org/c/coreboot/+/43673/4/src/soc/intel/jasperlake/in... PS4, Line 105: #define PMC_GPP_G 0x0 : #define PMC_GPP_B 0x1 : #define PMC_GPP_A 0x2 : #define PMC_GPP_R 0x3 : #define PMC_GPP_S 0x4 : #define PMC_GPD 0x5 : #define PMC_GPP_H 0x6 : #define PMC_GPP_D 0x7 : #define PMC_GPP_F 0x8 : #define PMC_GPP_C 0xA : #define PMC_GPP_E 0xB Can you please point me to the reference document for this mapping?
Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43673 )
Change subject: soc/intel/jasperlake: Fix PMC_GPE_DW mapping ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43673/4/src/soc/intel/jasperlake/in... File src/soc/intel/jasperlake/include/soc/pmc.h:
https://review.coreboot.org/c/coreboot/+/43673/4/src/soc/intel/jasperlake/in... PS4, Line 105: #define PMC_GPP_G 0x0 : #define PMC_GPP_B 0x1 : #define PMC_GPP_A 0x2 : #define PMC_GPP_R 0x3 : #define PMC_GPP_S 0x4 : #define PMC_GPD 0x5 : #define PMC_GPP_H 0x6 : #define PMC_GPP_D 0x7 : #define PMC_GPP_F 0x8 : #define PMC_GPP_C 0xA : #define PMC_GPP_E 0xB
Can you please point me to the reference document for this mapping?
Please refer to Jasper Lake PCH EDS XML. Doc# - 616935.
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43673 )
Change subject: soc/intel/jasperlake: Fix PMC_GPE_DW mapping ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43673/4/src/soc/intel/jasperlake/in... File src/soc/intel/jasperlake/include/soc/pmc.h:
https://review.coreboot.org/c/coreboot/+/43673/4/src/soc/intel/jasperlake/in... PS4, Line 105: #define PMC_GPP_G 0x0 : #define PMC_GPP_B 0x1 : #define PMC_GPP_A 0x2 : #define PMC_GPP_R 0x3 : #define PMC_GPP_S 0x4 : #define PMC_GPD 0x5 : #define PMC_GPP_H 0x6 : #define PMC_GPP_D 0x7 : #define PMC_GPP_F 0x8 : #define PMC_GPP_C 0xA : #define PMC_GPP_E 0xB
Please refer to Jasper Lake PCH EDS XML. Doc# - 616935.
For some reason, I am not able to find the doc in Intel's Technical Library.
Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43673 )
Change subject: soc/intel/jasperlake: Fix PMC_GPE_DW mapping ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43673/4/src/soc/intel/jasperlake/in... File src/soc/intel/jasperlake/include/soc/pmc.h:
https://review.coreboot.org/c/coreboot/+/43673/4/src/soc/intel/jasperlake/in... PS4, Line 105: #define PMC_GPP_G 0x0 : #define PMC_GPP_B 0x1 : #define PMC_GPP_A 0x2 : #define PMC_GPP_R 0x3 : #define PMC_GPP_S 0x4 : #define PMC_GPD 0x5 : #define PMC_GPP_H 0x6 : #define PMC_GPP_D 0x7 : #define PMC_GPP_F 0x8 : #define PMC_GPP_C 0xA : #define PMC_GPP_E 0xB
For some reason, I am not able to find the doc in Intel's Technical Library.
Checking on the same, Karthik. Will get back asap.
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43673 )
Change subject: soc/intel/jasperlake: Fix PMC_GPE_DW mapping ......................................................................
Patch Set 4: Code-Review+2
Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43673 )
Change subject: soc/intel/jasperlake: Fix PMC_GPE_DW mapping ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43673/4/src/soc/intel/jasperlake/in... File src/soc/intel/jasperlake/include/soc/pmc.h:
https://review.coreboot.org/c/coreboot/+/43673/4/src/soc/intel/jasperlake/in... PS4, Line 105: #define PMC_GPP_G 0x0 : #define PMC_GPP_B 0x1 : #define PMC_GPP_A 0x2 : #define PMC_GPP_R 0x3 : #define PMC_GPP_S 0x4 : #define PMC_GPD 0x5 : #define PMC_GPP_H 0x6 : #define PMC_GPP_D 0x7 : #define PMC_GPP_F 0x8 : #define PMC_GPP_C 0xA : #define PMC_GPP_E 0xB
Checking on the same, Karthik. Will get back asap.
Hi Karthik, is it okay to attach the snippet of the doc for code review? We are working on the access.
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43673 )
Change subject: soc/intel/jasperlake: Fix PMC_GPE_DW mapping ......................................................................
Patch Set 4: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/43673/4/src/soc/intel/jasperlake/in... File src/soc/intel/jasperlake/include/soc/pmc.h:
https://review.coreboot.org/c/coreboot/+/43673/4/src/soc/intel/jasperlake/in... PS4, Line 105: #define PMC_GPP_G 0x0 : #define PMC_GPP_B 0x1 : #define PMC_GPP_A 0x2 : #define PMC_GPP_R 0x3 : #define PMC_GPP_S 0x4 : #define PMC_GPD 0x5 : #define PMC_GPP_H 0x6 : #define PMC_GPP_D 0x7 : #define PMC_GPP_F 0x8 : #define PMC_GPP_C 0xA : #define PMC_GPP_E 0xB
Hi Karthik, is it okay to attach the snippet of the doc for code review? We are working on the acces […]
Please raise a bug and update it there once the access is granted.
Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43673 )
Change subject: soc/intel/jasperlake: Fix PMC_GPE_DW mapping ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43673/4/src/soc/intel/jasperlake/in... File src/soc/intel/jasperlake/include/soc/pmc.h:
https://review.coreboot.org/c/coreboot/+/43673/4/src/soc/intel/jasperlake/in... PS4, Line 105: #define PMC_GPP_G 0x0 : #define PMC_GPP_B 0x1 : #define PMC_GPP_A 0x2 : #define PMC_GPP_R 0x3 : #define PMC_GPP_S 0x4 : #define PMC_GPD 0x5 : #define PMC_GPP_H 0x6 : #define PMC_GPP_D 0x7 : #define PMC_GPP_F 0x8 : #define PMC_GPP_C 0xA : #define PMC_GPP_E 0xB
Please raise a bug and update it there once the access is granted.
Done. Please find the crosbug link here- https://partnerissuetracker.corp.google.com/u/0/issues/163679733
Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43673 )
Change subject: soc/intel/jasperlake: Fix PMC_GPE_DW mapping ......................................................................
Patch Set 4: Code-Review+2
Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43673 )
Change subject: soc/intel/jasperlake: Fix PMC_GPE_DW mapping ......................................................................
soc/intel/jasperlake: Fix PMC_GPE_DW mapping
PMC_GPE_DW mapping was not configured correctly and hence coreboot skipped programming Tier 1 GPIOs resulting in failure of S3 wake from Trackpad.
TEST=System should wake from S3 via trackpad
Change-Id: I59ce3720e0ffeefb2c9440bb300689def80211ea Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/43673 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Aamir Bohra aamir.bohra@intel.com Reviewed-by: Karthik Ramasubramanian kramasub@google.com Reviewed-by: Maulik V Vaghela maulik.v.vaghela@intel.com --- M src/soc/intel/jasperlake/gpio.c M src/soc/intel/jasperlake/include/soc/pmc.h 2 files changed, 13 insertions(+), 11 deletions(-)
Approvals: build bot (Jenkins): Verified Aamir Bohra: Looks good to me, approved Maulik V Vaghela: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved
diff --git a/src/soc/intel/jasperlake/gpio.c b/src/soc/intel/jasperlake/gpio.c index 3b3b262..22e73da 100644 --- a/src/soc/intel/jasperlake/gpio.c +++ b/src/soc/intel/jasperlake/gpio.c @@ -182,14 +182,15 @@ static const struct pmc_to_gpio_route routes[] = { { PMC_GPP_A, GPP_A }, { PMC_GPP_B, GPP_B }, + { PMC_GPP_G, GPP_G }, + { PMC_GPP_C, GPP_C }, { PMC_GPP_R, GPP_R }, { PMC_GPP_D, GPP_D }, { PMC_GPP_S, GPP_S }, { PMC_GPP_H, GPP_H }, + { PMC_GPP_F, GPP_F }, { PMC_GPD, GPP_GPD }, - { PMC_GPP_C, GPP_C }, - { PMC_GPP_E, GPP_E }, - { PMC_GPP_F, GPP_F } + { PMC_GPP_E, GPP_E } };
*num = ARRAY_SIZE(routes); diff --git a/src/soc/intel/jasperlake/include/soc/pmc.h b/src/soc/intel/jasperlake/include/soc/pmc.h index 5954a31..9eaa812 100644 --- a/src/soc/intel/jasperlake/include/soc/pmc.h +++ b/src/soc/intel/jasperlake/include/soc/pmc.h @@ -102,16 +102,17 @@ #define GPE0_DWX_MASK 0xf #define GPE0_DW_SHIFT(x) (4*(x))
-#define PMC_GPP_A 0x0 +#define PMC_GPP_G 0x0 #define PMC_GPP_B 0x1 -#define PMC_GPP_F 0x2 -#define PMC_GPD 0x3 -#define PMC_GPP_R 0x4 -#define PMC_GPP_S 0x6 +#define PMC_GPP_A 0x2 +#define PMC_GPP_R 0x3 +#define PMC_GPP_S 0x4 +#define PMC_GPD 0x5 +#define PMC_GPP_H 0x6 #define PMC_GPP_D 0x7 -#define PMC_GPP_C 0x8 -#define PMC_GPP_H 0xA -#define PMC_GPP_E 0xF +#define PMC_GPP_F 0x8 +#define PMC_GPP_C 0xA +#define PMC_GPP_E 0xB
#define GBLRST_CAUSE0 0x1924 #define GBLRST_CAUSE0_THERMTRIP (1 << 5)
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Aamir Bohra (Code Review) -
Karthik Ramasubramanian (Code Review)
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Maulik V Vaghela (Code Review)
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Meera Ravindranath (Code Review)
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Subrata Banik (Code Review)