Peichao Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43665 )
Change subject: mb/google/zork/vilboz: Enable P sensor ......................................................................
mb/google/zork/vilboz: Enable P sensor
BUG=b:161759253 TEST=flash the BIOS and insure firmware node will be generate under the OS.
Signed-off-by: Peichao.Wang peichao.wang@bitland.corp-partner.google.com Change-Id: I5e1a864bc156b434c39e8027fedf3a435757c1a7 --- M src/mainboard/google/zork/variants/vilboz/gpio.c M src/mainboard/google/zork/variants/vilboz/overridetree.cb 2 files changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/43665/1
diff --git a/src/mainboard/google/zork/variants/vilboz/gpio.c b/src/mainboard/google/zork/variants/vilboz/gpio.c index 4d292c2..29be3ae 100644 --- a/src/mainboard/google/zork/variants/vilboz/gpio.c +++ b/src/mainboard/google/zork/variants/vilboz/gpio.c @@ -9,6 +9,8 @@ static const struct soc_amd_gpio lte_gpio_set_stage_ram[] = { /* LTE POWER ENABLE */ PAD_GPO(GPIO_32, HIGH), + /* P sensor INT */ + PAD_SCI(GPIO_40, PULL_NONE, EDGE_LOW), };
diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb index 49d21d5..63d3f7d 100644 --- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb @@ -111,5 +111,12 @@ register "hid_desc_reg_offset" = "0x20" device i2c 2c on end end + chip drivers/i2c/generic + register "hid" = ""STH9324"" + register "name" = ""SEMTECH SX9324"" + register "desc" = ""SAR Proximity Sensor"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_40)" + device i2c 28 on end + end end end # chip soc/amd/picasso
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43665 )
Change subject: mb/google/zork/vilboz: Enable P sensor ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43665/1/src/mainboard/google/zork/v... File src/mainboard/google/zork/variants/vilboz/gpio.c:
https://review.coreboot.org/c/coreboot/+/43665/1/src/mainboard/google/zork/v... PS1, Line 13: PAD_SCI Why SCI?
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43665
to look at the new patch set (#2).
Change subject: mb/google/zork/vilboz: Enable P sensor ......................................................................
mb/google/zork/vilboz: Enable P sensor
BUG=b:161759253 TEST=flash the BIOS and insure firmware node will be generate under the OS.
Signed-off-by: Peichao.Wang peichao.wang@bitland.corp-partner.google.com Change-Id: I5e1a864bc156b434c39e8027fedf3a435757c1a7 --- M src/mainboard/google/zork/variants/vilboz/gpio.c M src/mainboard/google/zork/variants/vilboz/overridetree.cb 2 files changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/43665/2
Peichao Li has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43665 )
Change subject: mb/google/zork/vilboz: Enable P sensor ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43665/1/src/mainboard/google/zork/v... File src/mainboard/google/zork/variants/vilboz/gpio.c:
https://review.coreboot.org/c/coreboot/+/43665/1/src/mainboard/google/zork/v... PS1, Line 13: PAD_SCI
Why SCI?
SCI is unnecessary, I think PULL_LOW is ok.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43665 )
Change subject: mb/google/zork/vilboz: Enable P sensor ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43665/1/src/mainboard/google/zork/v... File src/mainboard/google/zork/variants/vilboz/gpio.c:
https://review.coreboot.org/c/coreboot/+/43665/1/src/mainboard/google/zork/v... PS1, Line 13: PAD_SCI
SCI is unnecessary
So, use PAD_INT?
I think PULL_LOW is ok.
Why PULL_LOW? This is active low signal. Is this actively driven by the P-sensor or open-drain signal? Is there an external pull-up?
Peichao Li has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43665 )
Change subject: mb/google/zork/vilboz: Enable P sensor ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43665/1/src/mainboard/google/zork/v... File src/mainboard/google/zork/variants/vilboz/gpio.c:
https://review.coreboot.org/c/coreboot/+/43665/1/src/mainboard/google/zork/v... PS1, Line 13: PAD_SCI
SCI is unnecessary […]
Dear Furquan, yes active low is correct, because these is a external pull-up resistor about 2.2k, thanks a lot.
Peichao Li has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43665 )
Change subject: mb/google/zork/vilboz: Enable P sensor ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43665/1/src/mainboard/google/zork/v... File src/mainboard/google/zork/variants/vilboz/gpio.c:
https://review.coreboot.org/c/coreboot/+/43665/1/src/mainboard/google/zork/v... PS1, Line 13: PAD_SCI
Dear Furquan, yes active low is correct, because these is a external pull-up resistor about 2. […]
Schematic like https://drive.google.com/file/d/1F00YyVT3c2dgQ-ytsK-49XxhlWgHhauf/view?usp=s...
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43665 )
Change subject: mb/google/zork/vilboz: Enable P sensor ......................................................................
Patch Set 2:
(4 comments)
https://review.coreboot.org/c/coreboot/+/43665/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43665/2//COMMIT_MSG@2 PS2, Line 2: peichao.wang Peichao Wang
https://review.coreboot.org/c/coreboot/+/43665/2//COMMIT_MSG@8 PS2, Line 8: Please quickly describe what the P sensor is.
https://review.coreboot.org/c/coreboot/+/43665/2//COMMIT_MSG@10 PS2, Line 10: insure firmware node will be generate : under the OS. … ensure OS generates firmware node by looking at the DSDT (acpidump?).
https://review.coreboot.org/c/coreboot/+/43665/2//COMMIT_MSG@13 PS2, Line 13: Peichao.Wang Peichao Wang
Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/43665?usp=email )
Change subject: mb/google/zork/vilboz: Enable P sensor ......................................................................
Abandoned