Change in coreboot[master]: soc/intel/denverton_ns: Add early SPI flash init

[Mariusz Szafrański (Code Review)]

Attention is currently required from: David Hendricks, Paul Menzel, Vanessa Eusebio, Michal Motyl, Patrick Rudolph, Felix Held.
Mariusz Szafrański has uploaded a new patch set (#3) to the change originally created by King Sumo. ( https://review.coreboot.org/c/coreboot/+/57033 )

Change subject: soc/intel/denverton_ns: Add early SPI flash init
......................................................................

soc/intel/denverton_ns: Add early SPI flash init

This change follows other Intel SoCs and adds early SPI flash init
in bootblock to allow SPI flash access in earlier stages.

This also fixes MRC cache write issue mentioned below.

Fast SPI initialization is required for MRC cache write. Due to the
missing initialization, the SPI transaction causes the assertion of the
FCERR error bit (BIOS_HSFSTS_CTL register), so the Flash writes are
failing.
(Takenover on author request)

Link: https://mail.coreboot.org/hyperkitty/list/[e-mail]/thread/W2E7G...
Change-Id: I50cc4f8ced0b0524b39eece5a2bb4f0d99fb4eff
Signed-off-by: Mariusz Szafranski 
---
M src/soc/intel/denverton_ns/bootblock/bootblock.c
1 file changed, 2 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/57033/3