New subject: [L] Change in coreboot[master]: mb/supermicro/x11-lga1151v2-series: Add x11sch-l4nf support

19 Aug 2020

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44578 )
Change subject: mb/supermicro/x11-lga1151v2-series: Add x11sch-l4nf support
......................................................................
mb/supermicro/x11-lga1151v2-series: Add x11sch-l4nf support
Add initial support for another CFL variant. Quite hacky right now - but
seems to boot Linux with Tianocore.
Right now I need to enable, but hidden, the two additional NICs. Not
sure where this comes from - maybe GPIOs.
Change-Id: I4c3d3aaf473ecc6106349245b5de1a6025ae0e9a
Signed-off-by: Christian Walter christian.walter@9elements.com
---
M src/mainboard/supermicro/x11-lga1151v2-series/Kconfig
M src/mainboard/supermicro/x11-lga1151v2-series/Kconfig.name
A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/Makefile.inc
A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/board_info.txt
A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/gpio.c
A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/include/variant/gpio.h
A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/include/variant/variants.h
A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/overridetree.cb
8 files changed, 460 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/44578/1

diff --git a/src/mainboard/supermicro/x11-lga1151v2-series/Kconfig b/src/mainboard/supermicro/x11-lga1151v2-series/Kconfig
index ed29b16..4029fce 100644
--- a/src/mainboard/supermicro/x11-lga1151v2-series/Kconfig
+++ b/src/mainboard/supermicro/x11-lga1151v2-series/Kconfig
@@ -25,6 +25,7 @@
 config MAINBOARD_PART_NUMBER
    string
    default "X11SCH-F"	if BOARD_SUPERMICRO_X11SCH_F
+	default "X11SCH-L4NF"	if BOARD_SUPERMICRO_X11SCH_L4NF
config MAINBOARD_DIR
    string
@@ -33,10 +34,12 @@
 config VARIANT_DIR
    string
    default "x11sch-f"	if BOARD_SUPERMICRO_X11SCH_F
+	default "x11sch-l4nf"	if BOARD_SUPERMICRO_X11SCH_L4NF
config MAINBOARD_PART_NUMBER
    string
    default "X11SCH-F"	if BOARD_SUPERMICRO_X11SCH_F
+	default "X11SCH-L4NF"	if BOARD_SUPERMICRO_X11SCH_L4NF
config MAX_CPUS
    int
diff --git a/src/mainboard/supermicro/x11-lga1151v2-series/Kconfig.name b/src/mainboard/supermicro/x11-lga1151v2-series/Kconfig.name
index 8ab4f1e..d25b19f 100644
--- a/src/mainboard/supermicro/x11-lga1151v2-series/Kconfig.name
+++ b/src/mainboard/supermicro/x11-lga1151v2-series/Kconfig.name
@@ -1,3 +1,8 @@
 config BOARD_SUPERMICRO_X11SCH_F
    bool "X11SCH-F"
    select BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151V2_SERIES
+
+config BOARD_SUPERMICRO_X11SCH_L4NF
+	bool "X11SCH-L4NF"
+	select BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151V2_SERIES
+
diff --git a/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/Makefile.inc b/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/Makefile.inc
new file mode 100644
index 0000000..8914639
--- /dev/null
+++ b/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/Makefile.inc
@@ -0,0 +1,2 @@
+bootblock-y += gpio.c
+ramstage-y += gpio.c
diff --git a/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/board_info.txt b/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/board_info.txt
new file mode 100644
index 0000000..a66959a
--- /dev/null
+++ b/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/board_info.txt
@@ -0,0 +1,7 @@
+Category: server
+Vendor name: Supermicro
+Board name: X11SCH-L4NF
+Board URL: https://www.supermicro.com/en/products/motherboard/X11SCH-F
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/gpio.c b/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/gpio.c
new file mode 100644
index 0000000..b2a72f5
--- /dev/null
+++ b/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/gpio.c
@@ -0,0 +1,296 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include "include/variant/gpio.h"
+#include <commonlib/helpers.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config gpio_table[] = {
+
+	/* ------- GPIO Community 0 ------- */
+
+	/* ------- GPIO Group GPP_A ------- */
+	_PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* ESPI_ALERT1# */
+	_PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* ESPI_IO0 */
+	_PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* ESPI_IO1 */
+	_PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* ESPI_IO2 */
+	_PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* ESPI_IO3 */
+	_PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* ESPI_CS0# */
+	_PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_A7, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* ESPI_ALERT0# */
+	_PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),	/* CLKRUN# */
+	_PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* ESPI_CLK */
+	_PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),	/* CLKOUT_LPC1 */
+	_PAD_CFG_STRUCT(GPP_A11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_A12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_A13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),	/* SUSWARN#/SUSPWRDNACK */
+	_PAD_CFG_STRUCT(GPP_A14, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* ESPI_RESET# */
+	_PAD_CFG_STRUCT(GPP_A15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* SUSACK# */
+	PAD_CFG_GPO(GPP_A16, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_A17, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_A18, NONE, DEEP, OFF, ACPI),	/* GPIO */
+	/* GPP_A19 - RESERVED */
+	_PAD_CFG_STRUCT(GPP_A20, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_A21, NONE, DEEP, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_A22, NONE, DEEP, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_A23, NONE, DEEP, OFF, ACPI),	/* GPIO */
+
+	/* ------- GPIO Group GPP_B ------- */
+	PAD_CFG_GPO(GPP_B0, 0, DEEP),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_B1, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_B2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),	/* GPIO */
+	PAD_CFG_GPO(GPP_B3, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_B4, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_B5, 0, DEEP),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_B6, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),	/* GPIO */
+	PAD_CFG_GPO(GPP_B7, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_B8, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_B9, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_B10, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_B11, 0, DEEP),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_B12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* SLP_S0# */
+	_PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* PLTRST# */
+	_PAD_CFG_STRUCT(GPP_B14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* SPKR */
+	PAD_CFG_GPO(GPP_B15, 1, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_B16, 1, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_B17, 0, DEEP),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_B18, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_B19, NONE, DEEP, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPO(GPP_B20, 1, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_B21, 1, DEEP),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_B22, NONE, DEEP, OFF, ACPI),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_B23, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* PCHHOT# */
+
+	/* ------- GPIO Community 1 ------- */
+
+	/* ------- GPIO Group GPP_C ------- */
+	/* GPP_C0 - RESERVED */
+	/* GPP_C1 - RESERVED */
+	_PAD_CFG_STRUCT(GPP_C2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),	/* GPIO */
+	/* GPP_C3 - RESERVED */
+	/* GPP_C4 - RESERVED */
+	PAD_CFG_GPO(GPP_C5, 0, DEEP),	/* GPIO */
+	/* GPP_C6 - RESERVED */
+	/* GPP_C7 - RESERVED */
+	_PAD_CFG_STRUCT(GPP_C8, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_C9, NONE, PLTRST, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPO(GPP_C10, 1, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_C11, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_C12, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_C13, 0, DEEP),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_C14, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),	/* GPIO */
+	PAD_CFG_GPO(GPP_C15, 0, DEEP),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_C16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0),	/* I2C0_SDA */
+	_PAD_CFG_STRUCT(GPP_C17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0),	/* I2C0_SCL */
+	_PAD_CFG_STRUCT(GPP_C18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0),	/* I2C1_SDA */
+	_PAD_CFG_STRUCT(GPP_C19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0),	/* I2C1_SCL */
+	/* GPP_C20 - RESERVED */
+	PAD_CFG_GPO(GPP_C21, 1, DEEP),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_C22, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_C23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),	/* GPIO */
+
+	/* ------- GPIO Group GPP_D ------- */
+	_PAD_CFG_STRUCT(GPP_D0, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),	/* GPIO */
+	PAD_CFG_GPO(GPP_D1, 1, PLTRST),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_D2, NONE, DEEP, OFF, ACPI),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_D3, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_D4, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),	/* GPIO */
+	PAD_CFG_GPO(GPP_D5, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_D6, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_D7, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_D8, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_D9, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_D10, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_D11, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_D12, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_D13, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_D14, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_D15, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_D16, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_D17, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_D18, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_D19, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_D20, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_D21, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_D22, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_D23, 0, DEEP),	/* GPIO */
+
+	/* ------- GPIO Group GPP_G ------- */
+	PAD_CFG_GPO(GPP_G0, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_G1, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_G2, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_G3, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_G4, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_G5, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_G6, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_G7, 0, DEEP),	/* GPIO */
+
+	/* ------- GPIO Group AZA ------- */
+
+	/* ------- GPIO Group VGPIO_0 ------- */
+
+	/* ------- GPIO Group VGPIO_1 ------- */
+
+	/* ------- GPIO Community 2 ------- */
+
+	/* ------- GPIO Group GPD ------- */
+	PAD_CFG_GPO(GPD0, 0, DEEP),	/* GPIO */
+	_PAD_CFG_STRUCT(GPD1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* ACPRESENT */
+	_PAD_CFG_STRUCT(GPD2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* LAN_WAKE# */
+	_PAD_CFG_STRUCT(GPD3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* PRWBTN# */
+	_PAD_CFG_STRUCT(GPD4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* SLP_S3# */
+	_PAD_CFG_STRUCT(GPD5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* SLP_S4# */
+	_PAD_CFG_STRUCT(GPD6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),	/* SLP_A# */
+	_PAD_CFG_STRUCT(GPD7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPD8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* SUSCLK */
+	PAD_CFG_GPO(GPD9, 0, DEEP),	/* GPIO */
+	_PAD_CFG_STRUCT(GPD10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* SLP_S5# */
+	PAD_CFG_GPO(GPD11, 0, DEEP),	/* GPIO */
+
+	/* ------- GPIO Community 3 ------- */
+
+	/* ------- GPIO Group GPP_K ------- */
+	_PAD_CFG_STRUCT(GPP_K0, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_K1, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_K2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_K3, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),	/* GPIO */
+	PAD_CFG_GPO(GPP_K4, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_K5, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_K6, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_K7, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_K8, NONE, DEEP, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPO(GPP_K9, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_K10, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_K11, 0, DEEP),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_K12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_K13, NONE, DEEP, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_K14, NONE, DEEP, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPO(GPP_K15, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_K16, 0, DEEP),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_K17, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),	/* GPIO */
+	PAD_CFG_GPO(GPP_K18, 1, DEEP),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_K19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* SMI# */
+	PAD_CFG_GPO(GPP_K20, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_K21, 0, DEEP),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_K22, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_K23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),	/* GPIO */
+
+	/* ------- GPIO Group GPP_H ------- */
+	PAD_CFG_GPO(GPP_H0, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_H1, 0, DEEP),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_H2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),	/* GPIO */
+	PAD_CFG_GPO(GPP_H3, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_H4, 0, DEEP),	/* GPIO */
+	/* GPP_H5 - RESERVED */
+	PAD_CFG_GPO(GPP_H6, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_H7, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_H8, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_H9, 0, DEEP),	/* GPIO */
+	/* GPP_H10 - RESERVED */
+	/* GPP_H11 - RESERVED */
+	PAD_CFG_GPO(GPP_H12, 1, PLTRST),	/* GPIO */
+	/* GPP_H13 - RESERVED */
+	/* GPP_H14 - RESERVED */
+	_PAD_CFG_STRUCT(GPP_H15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),	/* GPIO */
+	/* GPP_H16 - RESERVED */
+	/* GPP_H17 - RESERVED */
+	_PAD_CFG_STRUCT(GPP_H18, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),	/* GPIO */
+	PAD_CFG_GPO(GPP_H19, 1, PLTRST),	/* GPIO */
+	PAD_CFG_GPO(GPP_H20, 1, PLTRST),	/* GPIO */
+	PAD_CFG_GPO(GPP_H21, 1, PLTRST),	/* GPIO */
+	PAD_CFG_GPO(GPP_H22, 1, PLTRST),	/* GPIO */
+	PAD_CFG_GPO(GPP_H23, 0, DEEP),	/* GPIO */
+
+	/* ------- GPIO Group GPP_E ------- */
+	PAD_CFG_GPO(GPP_E0, 0, DEEP),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_E1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* SATAXPCIE1 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E2, NONE, DEEP, OFF, ACPI),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_E3, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),	/* GPIO */
+	PAD_CFG_GPO(GPP_E4, 0, DEEP),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_E5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_E6, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),	/* GPIO */
+	PAD_CFG_GPO(GPP_E7, 0, DEEP),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_E8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* SATALED# */
+	_PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* USB2_OC0# */
+	_PAD_CFG_STRUCT(GPP_E10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* USB2_OC1# */
+	_PAD_CFG_STRUCT(GPP_E11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* USB2_OC2# */
+	_PAD_CFG_STRUCT(GPP_E12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* USB2_OC3# */
+
+	/* ------- GPIO Group GPP_F ------- */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F0, NONE, DEEP, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F1, NONE, DEEP, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F2, NONE, DEEP, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F3, NONE, DEEP, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F4, NONE, DEEP, OFF, ACPI),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_F5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F6, NONE, DEEP, OFF, ACPI),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_F7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_F8, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_F9, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_F10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* SATA_SCLOCK */
+	_PAD_CFG_STRUCT(GPP_F11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* SATA_SLOAD */
+	_PAD_CFG_STRUCT(GPP_F12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* SATA_SDATAOUT1 */
+	_PAD_CFG_STRUCT(GPP_F13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* SATA_SDATAOUT0 */
+	PAD_CFG_GPO(GPP_F14, 0, DEEP),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_F15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* USB2_OC4# */
+	_PAD_CFG_STRUCT(GPP_F16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* USB2_OC5# */
+	PAD_CFG_GPO(GPP_F17, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_F18, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_F19, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_F20, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_F21, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_F22, 0, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_F23, 0, DEEP),	/* GPIO */
+
+	/* ------- GPIO Group SPI ------- */
+
+	/* ------- GPIO Community 4 ------- */
+
+	/* ------- GPIO Group GPP_I ------- */
+	_PAD_CFG_STRUCT(GPP_I0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)),	/* DDPB_HPD0 */
+	_PAD_CFG_STRUCT(GPP_I1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)),	/* DDPB_HPD1 */
+	_PAD_CFG_STRUCT(GPP_I2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)),	/* DDPB_HPD2 */
+	_PAD_CFG_STRUCT(GPP_I3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0),	/* DDPB_HPD3 */
+	_PAD_CFG_STRUCT(GPP_I4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0),	/* EDP_HPD */
+	_PAD_CFG_STRUCT(GPP_I5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0),	/* DDPB_CTRLCLK */
+	_PAD_CFG_STRUCT(GPP_I6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* DDPB_CTRLDATA */
+	_PAD_CFG_STRUCT(GPP_I7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0),	/* DDPC_CTRLCLK */
+	_PAD_CFG_STRUCT(GPP_I8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0),	/* DDPC_CTRLDATA */
+	_PAD_CFG_STRUCT(GPP_I9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PD)),	/* DDPD_CTRLCLK */
+	_PAD_CFG_STRUCT(GPP_I10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PD)),	/* DDPD_CTRLDATA */
+	_PAD_CFG_STRUCT(GPP_I11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)),	/* M2_SKT2_CFG0 */
+	_PAD_CFG_STRUCT(GPP_I12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)),	/* M2_SKT2_CFG1 */
+	_PAD_CFG_STRUCT(GPP_I13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)),	/* M2_SKT2_CFG2 */
+	_PAD_CFG_STRUCT(GPP_I14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)),	/* M2_SKT2_CFG3 */
+
+	/* ------- GPIO Group GPP_J ------- */
+	_PAD_CFG_STRUCT(GPP_J0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)),	/* CNV_PA_BLANKING */
+	_PAD_CFG_STRUCT(GPP_J1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)),	/* n/a */
+	_PAD_CFG_STRUCT(GPP_J2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* n/a */
+	_PAD_CFG_STRUCT(GPP_J3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* n/a */
+	PAD_CFG_GPI_TRIG_OWN(GPP_J4, NONE, DEEP, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_J5, NONE, DEEP, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_J6, NONE, DEEP, OFF, ACPI),	/* GPIO */
+	PAD_CFG_GPO(GPP_J7, 1, DEEP),	/* GPIO */
+	PAD_CFG_GPO(GPP_J8, 1, DEEP),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_J9, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_J10, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_J11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),	/* GPIO */
+};
+
+/* Early pad configuration in romstage. */
+const struct pad_config early_gpio_table[] = {
+	/*  GPP_B0 - Toggle SMBus mux to read DIMM SPDs */
+	PAD_CFG_GPO(GPP_B0, 1, DEEP),
+};
+
+const struct pad_config *get_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
+
+const struct pad_config *get_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
diff --git a/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/include/variant/gpio.h
new file mode 100644
index 0000000..018a08f
--- /dev/null
+++ b/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/include/variant/gpio.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef X11SCH_F_GPIO_H
+#define X11SCH_F_GPIO_H
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+#include <intelblocks/gpio_defs.h>
+
+const struct pad_config *get_gpio_table(size_t *num);
+const struct pad_config *get_early_gpio_table(size_t *num);
+
+#endif /* X11SCH_F__GPIO_H */
diff --git a/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/include/variant/variants.h b/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/include/variant/variants.h
new file mode 100644
index 0000000..b7ade58
--- /dev/null
+++ b/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/include/variant/variants.h
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/cnl_memcfg_init.h>
+
+/* Return memory configuration structure */
+const struct cnl_mb_cfg *variant_memcfg_config(void);
diff --git a/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/overridetree.cb b/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/overridetree.cb
new file mode 100644
index 0000000..9f936f5
--- /dev/null
+++ b/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/overridetree.cb
@@ -0,0 +1,128 @@
+chip soc/intel/cannonlake
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	# FSP configuration
+	register "SaGv" = "SaGv_Enabled"
+
+	register "SataSalpSupport" = "1"
+	register "SataPortsEnable[0]" = "1"
+	register "SataPortsEnable[1]" = "1"
+	register "SataPortsEnable[2]" = "1"
+	register "SataPortsEnable[3]" = "1"
+	register "SataPortsEnable[4]" = "1"
+	register "SataPortsEnable[5]" = "1"
+	register "SataPortsEnable[6]" = "1"
+	register "SataPortsEnable[7]" = "1"
+
+	register "PchHdaDspEnable" = "0"
+	register "PchHdaAudioLinkHda" = "1"
+
+	register "PcieRpEnable[1]" = "1"
+	register "PcieRpEnable[5]" = "1"
+	register "PcieRpEnable[8]" = "1"
+	register "PcieRpEnable[16]" = "1"
+	register "PcieRpEnable[20]" = "1"
+	register "PcieRpEnable[21]" = "1"
+	register "PcieRpEnable[22]" = "1"
+	register "PcieRpEnable[23]" = "1"
+
+	register "PcieClkSrcUsage[0]" = "0x80"
+	register "PcieClkSrcUsage[1]" = "0x80"
+	register "PcieClkSrcUsage[2]" = "0x80"
+	register "PcieClkSrcUsage[3]" = "0x80"
+	register "PcieClkSrcUsage[4]" = "0x80"
+	register "PcieClkSrcUsage[5]" = "0x80"
+	register "PcieClkSrcUsage[6]" = "0x80"
+	register "PcieClkSrcUsage[7]" = "0x80"
+	register "PcieClkSrcUsage[8]" = "0x80"
+	register "PcieClkSrcUsage[9]" = "0x80"
+	register "PcieClkSrcUsage[10]" = "0x80"
+	register "PcieClkSrcUsage[11]" = "0x80"
+	register "PcieClkSrcUsage[12]" = "0x80"
+	register "PcieClkSrcUsage[13]" = "0x80"
+	register "PcieClkSrcUsage[14]" = "0x80"
+	register "PcieClkSrcUsage[15]" = "0x80"
+
+	register "PcieClkSrcClkReq[0]" = "0"
+	register "PcieClkSrcClkReq[1]" = "1"
+	register "PcieClkSrcClkReq[2]" = "2"
+	register "PcieClkSrcClkReq[3]" = "3"
+	register "PcieClkSrcClkReq[4]" = "4"
+	register "PcieClkSrcClkReq[5]" = "5"
+	register "PcieClkSrcClkReq[6]" = "6"
+	register "PcieClkSrcClkReq[7]" = "7"
+	register "PcieClkSrcClkReq[8]" = "8"
+	register "PcieClkSrcClkReq[9]" = "9"
+	register "PcieClkSrcClkReq[10]" = "10"
+	register "PcieClkSrcClkReq[11]" = "11"
+	register "PcieClkSrcClkReq[12]" = "12"
+	register "PcieClkSrcClkReq[13]" = "13"
+	register "PcieClkSrcClkReq[14]" = "14"
+	register "PcieClkSrcClkReq[15]" = "15"
+
+	register "gen1_dec" = "0x000c0ca1"	# IPMI KCS
+
+	# USB Config 2.0/3.0
+
+	# USB OC0
+	register "usb2_ports[0]"	= "USB2_PORT_MID(OC0)"
+	register "usb2_ports[2]"	= "USB2_PORT_MID(OC0)"
+
+	# USB OC1
+	register "usb2_ports[1]"	= "USB2_PORT_MID(OC1)"
+	register "usb3_ports[3]"	= "USB3_PORT_DEFAULT(OC1)"
+
+	# USB OC2
+	register "usb2_ports[3]"	= "USB2_PORT_MID(OC2)"
+	register "usb2_ports[5]"	= "USB2_PORT_MID(OC2)"
+	register "usb3_ports[0]"	= "USB3_PORT_DEFAULT(OC2)"
+	register "usb3_ports[1]"	= "USB3_PORT_DEFAULT(OC2)"
+
+	# USB OC3
+	register "usb2_ports[4]"	= "USB2_PORT_MID(OC3)"
+	register "usb2_ports[6]"	= "USB2_PORT_MID(OC3)"
+
+	# USB OC4
+	register "usb2_ports[7]"	= "USB2_PORT_MID(OC4)"
+	register "usb2_ports[9]"	= "USB2_PORT_MID(OC4)"
+
+	# USB OC5
+	register "usb2_ports[8]"	= "USB2_PORT_MID(OC5)"
+	register "usb2_ports[10]"	= "USB2_PORT_MID(OC5)"
+	register "usb3_ports[2]"	= "USB3_PORT_DEFAULT(OC5)"
+	register "usb3_ports[4]"	= "USB3_PORT_DEFAULT(OC5)"
+
+	# USB KCS
+	register "usb2_ports[13]"	= "USB2_PORT_MID(OC_SKIP)"
+
+	# USB OC6/7 - not connected
+
+	# Enable "Intel Speed Shift Technology"
+	register "speed_shift_enable" = "1"
+
+	# HECI
+	register "HeciEnabled" = "1"
+	# SPS doesn't support all command issued by FSP...
+	register "DisableHeciRetry" = "1"
+
+	# Internal GFX
+	register "InternalGfx" = "1"
+
+	# Disable S0ix
+	register "s0ix_enable" = "0"
+
+	device domain 0 on
+		device pci 1b.0 hidden  end # PCIe Bridge
+		device pci 1b.4 on  end # onboard Ethernet
+		device pci 1b.5 on  end # onboard Ethernet
+		device pci 1b.6 hidden  end # onboard Ethernet
+		device pci 1b.7 hidden  end # onboard Ethernet
+		device pci 1c.0 on  end # PCIe Bridge
+		device pci 1c.1 on  end # Aspeed Graphics
+		device pci 1c.4 on  end # NVMe PCIE x4
+		device pci 1d.0 on  end # PCIE x4
+	end
+end
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I4c3d3aaf473ecc6106349245b5de1a6025ae0e9a
Gerrit-Change-Number: 44578
Gerrit-PatchSet: 1
Gerrit-Owner: Christian Walter christian.walter@9elements.com
Gerrit-MessageType: newchange



    