Change in coreboot[master]: soc/intel/denverton_ns: Implement PCIe post config + lock

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25442 )

Change subject: soc/intel/denverton_ns: Implement PCIe post config + lock
......................................................................

Patch Set 3: Verified+1

Build Successful

https://qa.coreboot.org/job/coreboot-gerrit/69521/ : SUCCESS

https://qa.coreboot.org/job/coreboot-checkpatch/23837/ : SUCCESS