Change in coreboot[master]: soc/amd/stoneyridge: Add IOMMU support

[Marc Jones (Code Review)]

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/28753

Change subject: soc/amd/stoneyridge: Add IOMMU support
......................................................................

soc/amd/stoneyridge: Add IOMMU support

Enable the IOMMU in AGESA and copy the AGESA generated IVRS ACPI table.

BUG=b:116196614
TEST=Check dmesg for AMD-Vi messages.

Change-Id: I688d867c7bd4949a57b27c1b6a793c6a6e4a717a
Signed-off-by: Marc Jones 
---
M src/include/device/pci_ids.h
M src/soc/amd/common/block/pi/agesawrapper.c
M src/soc/amd/stoneyridge/Makefile.inc
A src/soc/amd/stoneyridge/iommu.c
M src/soc/amd/stoneyridge/northbridge.c
5 files changed, 66 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/28753/1

diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index a6ed6d9..3de1e85 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -298,6 +298,7 @@
 #define PCI_DEVICE_ID_AMD_15H_NB_IOMMU		0x1419
 #define PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_IOMMU	0x1423
 #define PCI_DEVICE_ID_AMD_16H_MODEL_303F_NB_IOMMU	0x1567
+#define PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_IOMMU	0x1577

#define PCI_DEVICE_ID_ATI_SB600_LPC		0x438D
 #define PCI_DEVICE_ID_ATI_SB600_SATA		0x4380
diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c
index 5cd04ba..fdde226 100644
--- a/src/soc/amd/common/block/pi/agesawrapper.c
+++ b/src/soc/amd/common/block/pi/agesawrapper.c
@@ -321,6 +321,9 @@
     */
    AMD_LATE_PARAMS *LateParams = create_struct(&AmdParamStruct);

+	LateParams->GnbLateConfiguration.GnbIoapicId = CONFIG_MAX_CPUS + 1;
+	LateParams->GnbLateConfiguration.FchIoapicId = CONFIG_MAX_CPUS;
+
    timestamp_add_now(TS_AGESA_INIT_LATE_START);
    Status = AmdInitLate(LateParams);
    timestamp_add_now(TS_AGESA_INIT_LATE_DONE);
diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc
index a8db2c2..c54b652 100644
--- a/src/soc/amd/stoneyridge/Makefile.inc
+++ b/src/soc/amd/stoneyridge/Makefile.inc
@@ -97,6 +97,7 @@
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
 ramstage-y += gpio.c
 ramstage-y += hda.c
+ramstage-y += iommu.c
 ramstage-y += monotonic_timer.c
 ramstage-y += southbridge.c
 ramstage-y += sb_util.c
diff --git a/src/soc/amd/stoneyridge/iommu.c b/src/soc/amd/stoneyridge/iommu.c
new file mode 100644
index 0000000..8c45457
--- /dev/null
+++ b/src/soc/amd/stoneyridge/iommu.c
@@ -0,0 +1,60 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Rudolf Marek 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <lib.h>
+
+static void iommu_read_resources(struct device *dev)
+{
+	struct resource *res;
+
+	/* Get the normal pci resources of this device */
+	pci_dev_read_resources(dev);
+
+	/* Add an extra subtractive resource for both memory and I/O. */
+	res = new_resource(dev, 0x44);
+	res->size = 512 * 1024;
+	res->align = log2(res->size);
+	res->gran = log2(res->size);
+	res->limit = 0xffffffff;	/* 4G */
+	res->flags = IORESOURCE_MEM;
+}
+
+static void iommu_set_resources(struct device *dev)
+{
+	pci_dev_set_resources(dev);
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = pci_dev_set_subsystem,
+};
+
+static struct device_operations iommu_ops = {
+	.read_resources = iommu_read_resources,
+	.set_resources = iommu_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init = 0,
+	.scan_bus = 0,
+	.ops_pci = &lops_pci,
+};
+
+static const struct pci_driver iommu_driver __pci_driver = {
+	.ops = &iommu_ops,
+	.vendor = PCI_VENDOR_ID_AMD,
+	.device = PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_IOMMU,
+};
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index 912daa0..95c2a07 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -508,7 +508,7 @@

void SetNbEnvParams(GNB_ENV_CONFIGURATION *params)
 {
-	params->IommuSupport = FALSE;
+	params->IommuSupport = TRUE;
    set_board_env_params(params);
 }