[XS] Change in coreboot[main]: nb/intel/sandybridge/raminit: Set SRT on Sandy Bridge

[Angel Pons (Code Review)]

Attention is currently required from: Patrick Rudolph, Paul Menzel.

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79784?usp=email )

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Change subject: nb/intel/sandybridge/raminit: Set SRT on Sandy Bridge
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Patch Set 3:

(1 comment)

File src/northbridge/intel/sandybridge/raminit_common.c:

https://review.coreboot.org/c/coreboot/+/79784/comment/82f25397_eb223d41 :
PS3, Line 784: if ((IS_IVY_CPU(ctrl->cpu) && ctrl->tCK >= TCK_1066MHZ) ||
             : 	    IS_SANDY_CPU(ctrl->cpu))
I believe the tCK check is to improve stability at high clock speeds. Sandy Bridge needs to be overclocked quite a bit to run at 1066 MHz (DDR3-2133), and it's likely it would benefit from SRT being disabled. So, we could simplify this check to `ctrl->tCK >= TCK_1066MHZ`.