Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jeff Daly, Jérémy Compostella, Kapil Porwal, Lean Sheng Tan, Nick Vaccaro, Sean Rhodes, Subrata Banik, Tarun, Vanessa Eusebio, Werner Zeh.
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83065?usp=email )
Change subject: cpu/x86: Select proper SMM save Kconfig option ......................................................................
cpu/x86: Select proper SMM save Kconfig option
Note: Qemu always uses AMD64 save states but messes up the revision if the CPU is set to be a 32bit-only one the save state revision is 0 but still uses the AMD64 one. This is currently not handled by coreboot.
Note2: The apollolake and denverton_ns code suggests that em64t100 should be used but I was told the documentation says em64t101. Select both to be sure.
Change-Id: If045a04b6617eefc79a117486a9b224f4ca96b17 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/haswell/Kconfig M src/cpu/intel/model_1067x/Kconfig M src/cpu/intel/model_106cx/Kconfig M src/cpu/intel/model_2065x/Kconfig M src/cpu/intel/model_206ax/Kconfig M src/cpu/intel/model_f2x/Kconfig M src/cpu/intel/model_f3x/Kconfig M src/cpu/intel/model_f4x/Kconfig M src/cpu/intel/slot_1/Kconfig M src/cpu/intel/socket_441/Kconfig M src/cpu/intel/socket_BGA956/Kconfig M src/cpu/intel/socket_LGA775/Kconfig M src/cpu/intel/socket_m/Kconfig M src/cpu/intel/socket_mPGA604/Kconfig M src/cpu/x86/Kconfig M src/mainboard/emulation/qemu-i440fx/Kconfig M src/mainboard/emulation/qemu-q35/Kconfig M src/soc/intel/alderlake/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/meteorlake/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/tigerlake/Kconfig 29 files changed, 37 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/83065/1
diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index b66a4aa..1f937a7 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -15,6 +15,7 @@ select CPU_INTEL_COMMON_TIMEBASE select HAVE_ASAN_IN_ROMSTAGE select CPU_INTEL_COMMON_VOLTAGE + select X86_EM64T101_SAVE_STATE
if CPU_INTEL_HASWELL
diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig index 721e0e9..e3bbcdf 100644 --- a/src/cpu/intel/model_1067x/Kconfig +++ b/src/cpu/intel/model_1067x/Kconfig @@ -12,3 +12,4 @@ select CPU_INTEL_COMMON_TIMEBASE select SETUP_XIP_CACHE select EDK2_USE_LAPIC_TIMER if PAYLOAD_EDK2 + select X86_EM64T101_SAVE_STATE diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index 0a68a31..2685125 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -12,3 +12,5 @@ select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE + select X86_LEGACY_SAVE_STATE + select X86_EM64T101_SAVE_STATE diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 2b9c4b2..474c11d 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -13,6 +13,7 @@ select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE select CPU_INTEL_COMMON_VOLTAGE + select X86_EM64T101_SAVE_STATE
if CPU_INTEL_MODEL_2065X
diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index cf16640..89907db 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -12,6 +12,7 @@ select TSC_SYNC_MFENCE select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE + select X86_EM64T101_SAVE_STATE
if CPU_INTEL_MODEL_206AX
diff --git a/src/cpu/intel/model_f2x/Kconfig b/src/cpu/intel/model_f2x/Kconfig index e05ba6f..0a6747b 100644 --- a/src/cpu/intel/model_f2x/Kconfig +++ b/src/cpu/intel/model_f2x/Kconfig @@ -6,3 +6,5 @@ select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON select SSE2 + select X86_LEGACY_SAVE_STATE + select X86_EM64T101_SAVE_STATE diff --git a/src/cpu/intel/model_f3x/Kconfig b/src/cpu/intel/model_f3x/Kconfig index 229ddb0..120d104 100644 --- a/src/cpu/intel/model_f3x/Kconfig +++ b/src/cpu/intel/model_f3x/Kconfig @@ -6,3 +6,5 @@ select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON select SSE2 + select X86_LEGACY_SAVE_STATE + select X86_EM64T101_SAVE_STATE diff --git a/src/cpu/intel/model_f4x/Kconfig b/src/cpu/intel/model_f4x/Kconfig index a7332e0..c13afba 100644 --- a/src/cpu/intel/model_f4x/Kconfig +++ b/src/cpu/intel/model_f4x/Kconfig @@ -5,3 +5,4 @@ select ARCH_X86 select SUPPORT_CPU_UCODE_IN_CBFS select SSE2 + select X86_EM64T101_SAVE_STATE diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index fffca39..e524fcf 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -13,6 +13,7 @@ select UNKNOWN_TSC_RATE select SETUP_XIP_CACHE select RESERVE_MTRRS_FOR_OS + select X86_LEGACY_SAVE_STATE
if CPU_INTEL_SLOT_1
diff --git a/src/cpu/intel/socket_441/Kconfig b/src/cpu/intel/socket_441/Kconfig index b5bbc2d..04dedae 100644 --- a/src/cpu/intel/socket_441/Kconfig +++ b/src/cpu/intel/socket_441/Kconfig @@ -4,6 +4,7 @@ bool select CPU_INTEL_MODEL_106CX select SETUP_XIP_CACHE + select X86_EM64T101_SAVE_STATE
if CPU_INTEL_SOCKET_441
diff --git a/src/cpu/intel/socket_BGA956/Kconfig b/src/cpu/intel/socket_BGA956/Kconfig index 19637c3..afda6d7 100644 --- a/src/cpu/intel/socket_BGA956/Kconfig +++ b/src/cpu/intel/socket_BGA956/Kconfig @@ -3,6 +3,7 @@ config CPU_INTEL_SOCKET_BGA956 bool select CPU_INTEL_MODEL_1067X + select X86_EM64T101_SAVE_STATE
if CPU_INTEL_SOCKET_BGA956
diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig index e192d22..8dc58ef 100644 --- a/src/cpu/intel/socket_LGA775/Kconfig +++ b/src/cpu/intel/socket_LGA775/Kconfig @@ -7,6 +7,7 @@ select CPU_INTEL_MODEL_F4X select CPU_INTEL_MODEL_1067X select SIPI_VECTOR_IN_ROM + select X86_EM64T101_SAVE_STATE
if CPU_INTEL_SOCKET_LGA775
diff --git a/src/cpu/intel/socket_m/Kconfig b/src/cpu/intel/socket_m/Kconfig index 62402a1..2655201 100644 --- a/src/cpu/intel/socket_m/Kconfig +++ b/src/cpu/intel/socket_m/Kconfig @@ -4,6 +4,8 @@ bool select CPU_INTEL_MODEL_6EX select CPU_INTEL_MODEL_6FX + select X86_LEGACY_SAVE_STATE + select X86_EM64T101_SAVE_STATE
if CPU_INTEL_SOCKET_M
diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index 81faca7..7368841 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -8,6 +8,7 @@ select SIPI_VECTOR_IN_ROM select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE + select X86_EM64T101_SAVE_STATE
if CPU_INTEL_SOCKET_MPGA604
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index fbcb0e2..6f71a16 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -199,6 +199,7 @@
config X86_AMD64_SAVE_STATE bool + default y if CPU_AMD_PI || SOC_AMD_COMMON help Select this on platforms that have CPUs with a AMD64 save state area. diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index 24dfa7a2..a831cc9 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -19,6 +19,8 @@ select NO_SMM select BOOT_DEVICE_NOT_SPI_FLASH select BOOT_DEVICE_MEMORY_MAPPED + select X86_AMD64_SAVE_STATE + select X86_LEGACY_SAVE_STATE
config VBOOT select VBOOT_MUST_REQUEST_DISPLAY diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index 11ea750..bc9ba4b 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -17,6 +17,8 @@ select MAINBOARD_HAS_CHROMEOS select BOOT_DEVICE_NOT_SPI_FLASH select BOOT_DEVICE_MEMORY_MAPPED + select X86_AMD64_SAVE_STATE + select X86_LEGACY_SAVE_STATE
config VBOOT select VBOOT_MUST_REQUEST_DISPLAY diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index eb5b8c0..19e7cb0 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -96,6 +96,7 @@ select UDK_202005_BINDING if !SOC_INTEL_ALDERLAKE_PCH_N select VBOOT_LIB select X86_CLFLUSH_CAR + select X86_EM64T101_SAVE_STATE help Intel Alderlake support. Mainboards should specify the PCH type using the `SOC_INTEL_ALDERLAKE_PCH_*` options instead diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 61aaa44..bf175c9 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -83,6 +83,8 @@ # This SoC does not map SPI flash like many previous SoC. Therefore we # provide a custom media driver that facilitates mapping select X86_CUSTOM_BOOTMEDIA + select X86_EM64T100_SAVE_STATE # TODO is this true? + select X86_EM64T101_SAVE_STATE help Intel Apollolake support
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 09fdbba..ca0e999 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -34,6 +34,7 @@ select TCO_SPACE_NOT_YET_SPLIT select USE_DDR3 select NEED_SMALL_2MB_PAGE_TABLES + select X86_EM64T100_SAVE_STATE help Bay Trail M/D part support.
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 9b96d11..194d007 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -40,6 +40,7 @@ select NO_CBFS_MCACHE select TCO_SPACE_NOT_YET_SPLIT select NEED_SMALL_2MB_PAGE_TABLES + select X86_EM64T100_SAVE_STATE help Braswell M/D part support.
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 4859a7e..bda187e 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -9,6 +9,7 @@ select REG_SCRIPT select TCO_SPACE_NOT_YET_SPLIT select INTEL_LYNXPOINT_LP + select X86_EM64T100_SAVE_STATE help Intel Broadwell and Haswell ULT support.
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 3aa06f4..e21e508 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -75,6 +75,7 @@ select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE select X86_CLFLUSH_CAR + select X86_EM64T101_SAVE_STATE
config SOC_INTEL_COFFEELAKE bool diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 55ba2cd..a74ada3 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -39,6 +39,8 @@ select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE + select X86_EM64T100_SAVE_STATE # TODO is this true? + select X86_EM64T101_SAVE_STATE help Intel Denverton-NS SoC support
diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 9bee9be..4991c9a 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -65,6 +65,7 @@ select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM select SOC_INTEL_RAPL_DISABLE_VIA_MCHBAR select X86_CLFLUSH_CAR + select X86_EM64T101_SAVE_STATE help Intel Elkhartlake support
diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 2871508..a043c0c 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -70,6 +70,7 @@ select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE select SOC_INTEL_COMMON_BASECODE if SOC_INTEL_CSE_LITE_SKU + select X86_EM64T101_SAVE_STATE help Intel Jasperlake support
diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 622d35f..52c4d90 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -106,6 +106,7 @@ select UDK_202302_BINDING select X86_CLFLUSH_CAR select X86_INIT_NEED_1_SIPI + select X86_EM64T101_SAVE_STATE select INTEL_KEYLOCKER help Intel Meteorlake support. Mainboards should specify the SoC diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 3ec84ab..719ff98 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -72,6 +72,7 @@ select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE + select X86_EM64T101_SAVE_STATE
config SOC_INTEL_SKYLAKE bool diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 59f54aa..f12d1d6 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -90,6 +90,7 @@ select SOC_INTEL_COMMON_BASECODE_RAMTOP select CR50_USE_LONG_INTERRUPT_PULSES if TPM_GOOGLE_CR50 select X86_CLFLUSH_CAR + select X86_EM64T101_SAVE_STATE help Intel Tigerlake support
-
Arthur Heymans (Code Review)