Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74845 )
Change subject: soc/amd/common/block/lpc/lpc: report eSPI MMIO ......................................................................
soc/amd/common/block/lpc/lpc: report eSPI MMIO
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: I63fb70da3e9ded6c05354f94ee69bc6dd04e58f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74845 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Matt DeVillier matt.devillier@amd.corp-partner.google.com Reviewed-by: Arthur Heymans arthur@aheymans.xyz --- M src/soc/amd/common/block/lpc/lpc.c 1 file changed, 18 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Matt DeVillier: Looks good to me, but someone else must approve
diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index 5b836ea..edc7476 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -123,7 +123,10 @@ /* Add a memory resource for the SPI BAR. */ mmio_range(dev, 2, SPI_BASE_ADDRESS, 4 * KiB);
- res = new_resource(dev, 3); /* IOAPIC */ + /* Add a memory resource for the eSPI MMIO */ + mmio_range(dev, 3, SPI_BASE_ADDRESS + ESPI_OFFSET_FROM_BAR, 4 * KiB); + + res = new_resource(dev, 4); /* IOAPIC */ res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;