Petr Cvek has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35737 )
Change subject: sb/intel/i82801gx: Correctly align register offset ......................................................................
Patch Set 2:
(5 comments)
will be changed in next version
https://review.coreboot.org/c/coreboot/+/35737/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35737/2//COMMIT_MSG@7 PS2, Line 7: Correctly align register offset
The register is simply wrong, but include/device/pci_mmio_cfg. […]
Ack
https://review.coreboot.org/c/coreboot/+/35737/2//COMMIT_MSG@10 PS2, Line 10:
Please add to the commit message, if this fixes an actual problem, and how this is tested.
Ack
https://review.coreboot.org/c/coreboot/+/35737/2/src/southbridge/intel/i8280... File src/southbridge/intel/i82801gx/sata.c:
https://review.coreboot.org/c/coreboot/+/35737/2/src/southbridge/intel/i8280... PS2, Line 97: u32
define as u8 *
Ack
https://review.coreboot.org/c/coreboot/+/35737/2/src/southbridge/intel/i8280... PS2, Line 158: ahci_
struct resource *ahci_res = find_resource(dev, PCI_BASE_ADDRESS_5); […]
Ack
https://review.coreboot.org/c/coreboot/+/35737/2/src/southbridge/intel/i8280... PS2, Line 158: 0x24
PCI_BASE_ADDRESS_5
if a generic name PCI_BASE_ADDRESS_5 is OK, I'm gonna change the rest of reg 0x24 references in this file to it too.
-
Petr Cvek (Code Review)