New patch to review for coreboot: imgtec/pistachio: Fix memlayout ASSERT with new binutils
Stefan Reinauer (stefan.reinauer@coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14440
-gerrit
commit aae7c2dec8f5d45ac6cb96af25098c660a48830b Author: Stefan Reinauer stefan.reinauer@coreboot.org Date: Wed Apr 20 09:33:30 2016 -0700
imgtec/pistachio: Fix memlayout ASSERT with new binutils
With binutils 2.26 our memlayout ASSERT for mirrored SRAM regions gets confused due to the lack of parentheses grouping the expressions.
This fixes the following issue:
LINK cbfs/fallback/bootblock.debug mipsel-elf-ld.bfd: bootblock and gram_bootblock do not match! mipsel-elf-ld.bfd: romstage and kseg0_romstage do not match!
Change-Id: Ib406e229b8a552d9ffc4538b55ee0269bfed62a8 Signed-off-by: Stefan Reinauer stefan.reinauer@coreboot.org --- src/soc/imgtec/pistachio/include/soc/memlayout.ld | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld index 9891bae..05042ef 100644 --- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld +++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld @@ -20,8 +20,8 @@ /* SRAM memory is mapped in two different locations. Define regions in both for * full overlap checking and use this to guarantee they're kept in sync. */ #define ASSERT_MIRRORED(r1, r2) \ - _ = ASSERT(_e##r1 - _##r1 == _e##r2 - _##r2 && \ - _##r1 & 0x7fffffff == _##r2 & 0x7fffffff, \ + _ = ASSERT((_e##r1 - _##r1) == (_e##r2 - _##r2) && \ + (_##r1 & 0x7fffffff) == (_##r2 & 0x7fffffff), \ STR(r1 and r2 do not match!));
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Stefan Reinauer