Patch set updated for coreboot: 567c135 asrock/e350m1/mainboard.c: Power unused GPP PCIe clock pins off

[Paul Menzel]

Paul Menzel ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5397

-gerrit

commit 567c13512dc1fb289d3572907ab289b7c910bb7a
Author: Paul Menzel 
Date:   Sat Mar 22 23:22:29 2014 +0100

asrock/e350m1/mainboard.c: Power unused GPP PCIe clock pins off

According to the SB800 Register Reference Guide [1] the clock pins are
    powered on (0xFF) by default. On the ASRock E350M1 not all GPP PCIe
    devices are used, so power their clock pins off as there is no point in
    leaving them enabled.

The same is done for the board AMD Persimmon in commit 73be43a1 [2].

Persimmon: Disable the unused GPP PCIe clocks

Note that the board AMD Persimmon has a normal PCI slot, where the
    ASRock E350M1 has a PCIe 2.0 x16 slot, usable for example for external
    graphics cards. So leave the clock pins for the Gfx PCIe device
    powered on.

[1] AMD SB800-Series Southbridges Register Reference Guide
        Publication: #45482
        Revision: 3.04
    [2] http://review.coreboot.org/1876

Change-Id: Ibd839bb469f06cbbb8a50d6a0bc58ad967a1a5e1
    Fix-proposed-by: Edward O'Callaghan 
    Signed-off-by: Paul Menzel 
---
 src/mainboard/asrock/e350m1/mainboard.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/src/mainboard/asrock/e350m1/mainboard.c b/src/mainboard/asrock/e350m1/mainboard.c
index a98a179..61dcc33 100644
--- a/src/mainboard/asrock/e350m1/mainboard.c
+++ b/src/mainboard/asrock/e350m1/mainboard.c
@@ -25,6 +25,8 @@
 #include <cpu/amd/mtrr.h>
 #include <device/pci_def.h>
 #include <southbridge/amd/cimx/cimx_util.h>
+#include <agesawrapper.h>
+#include "SBPLATFORM.h"

//#define SMBUS_IO_BASE 0x6000
 void set_pcie_reset(void);
@@ -54,6 +56,15 @@ static void mainboard_enable(device_t dev)
 {
    printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");

+	/* enable GPP CLK0 thru CLK3 and SLT_GFX_CLK (interleaved) */
+	/* disable GPP CLK4 thru GPP CLK8 */
+	u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE);
+	*(misc_mem_clk_cntrl + 0) = 0xFF;
+	*(misc_mem_clk_cntrl + 1) = 0xFF;
+	*(misc_mem_clk_cntrl + 2) = 0x00;
+	*(misc_mem_clk_cntrl + 3) = 0x00;
+	*(misc_mem_clk_cntrl + 4) = 0xF0;
+
    /*
     * Initialize ASF registers to an arbitrary address because someone
     * long ago set things up this way inside the SPD read code.  The