Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50427 )
Change subject: [RFC] soc/intel/cannonlake: Enable EIST for all boards ......................................................................
[RFC] soc/intel/cannonlake: Enable EIST for all boards
Invert the `eist_enabled` option and do not set it anywhere. Can we do this? Does any board require EIST to be disabled?
Change-Id: Iae5dd655eca36779db89929c0020b994e69e0f8d Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb M src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb M src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb M src/mainboard/system76/lemp9/devicetree.cb M src/mainboard/system76/oryp5/devicetree.cb M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/cpu.c 8 files changed, 3 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/50427/1
diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index 4a93065..6fe8b89 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -19,9 +19,6 @@ .tdp_pl2_override = 30, }"
- # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" - # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "SaGv" = "SaGv_Enabled" #register "enable_c6dram" = "1" diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb index 4d35c47..d38a62f 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb +++ b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb @@ -134,9 +134,6 @@ # Disable S0ix register "s0ix_enable" = "0"
- # Enable Turbo - register "eist_enable" = "1" - register "common_soc_config" = "{ .gspi[0] = { .speed_mhz = 1, diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb index 8fb84ce..b9865db 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb @@ -11,9 +11,6 @@ .tdp_pl2_override = 28, }"
- # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" - # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "SaGv" = "SaGv_FixedHigh"
diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb index 3a0758a..dcb8b7d 100644 --- a/src/mainboard/system76/lemp9/devicetree.cb +++ b/src/mainboard/system76/lemp9/devicetree.cb @@ -19,9 +19,6 @@ .tdp_pl2_override = 30, }"
- # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" - # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "SaGv" = "SaGv_Enabled" #register "enable_c6dram" = "1" diff --git a/src/mainboard/system76/oryp5/devicetree.cb b/src/mainboard/system76/oryp5/devicetree.cb index 6cf5c94..1a8767d 100644 --- a/src/mainboard/system76/oryp5/devicetree.cb +++ b/src/mainboard/system76/oryp5/devicetree.cb @@ -16,9 +16,6 @@ .tdp_pl2_override = 78, }"
- # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" - # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "enable_c6dram" = "1"
diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 5b09b48..a9c5ab9 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -142,7 +142,7 @@ config_t *config = config_of_soc();
/* Generate P-state tables */ - if (config->eist_enable) + if (!config->eist_disable) generate_p_state_entries(core_id, cores_per_package); }
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 15592d5..685714a 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -230,8 +230,7 @@ * 11b - Reserved */ uint8_t SendVrMbxCmd;
- /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ - uint8_t eist_enable; + uint8_t eist_disable;
/* Enable C6 DRAM */ uint8_t enable_c6dram; diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 6a4f773..d8f5cf7 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -37,7 +37,7 @@ wrmsr(IA32_MISC_ENABLE, msr);
/* Set EIST status */ - cpu_set_eist(conf->eist_enable); + cpu_set_eist(!conf->eist_disable);
/* Disable Thermal interrupts */ msr.lo = 0;