Change in coreboot[master]: soc/intel/tigerlake: Skip Gpio configuration from FSP

[Srinidhi N Kaushik (Code Review)]

Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44913 )

Change subject: soc/intel/tigerlake: Skip Gpio configuration from FSP
......................................................................

soc/intel/tigerlake: Skip Gpio configuration from FSP

FSP v3333 or later, provides a new UPD to Skip configuring
Gpio settings from FSP. Coreboot should provide all the
required Gpio configuration for the platform when this UPD
is set.

BUG=b:166790597, 146390704
BRANCH=none
TEST=build and boot volteer proto2

Signed-off-by: Srinidhi N Kaushik 
Change-Id: If32f35a188d510db8e4d8973cae78297d49a9240
---
M src/soc/intel/tigerlake/romstage/fsp_params.c
1 file changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/44913/1

diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c
index 2ba276d..4b68cb6 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params.c
@@ -87,6 +87,9 @@
    dev = pcidev_path_on_root(PCH_DEVFN_ISH);
    m_cfg->PchIshEnable = is_dev_enabled(dev);

+	/* Skip GPIO configuration from FSP */
+	m_cfg->GpioOverride = 0x1;
+
    /* DP port config */
    m_cfg->DdiPortAConfig = config->DdiPortAConfig;
    m_cfg->DdiPortBConfig = config->DdiPortBConfig;

[Srinidhi N Kaushik (Code Review)]

Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44913 )

Change subject: soc/intel/tigerlake: Skip Gpio configuration from FSP
......................................................................

Patch Set 1: Code-Review+1

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44913 )

Change subject: soc/intel/tigerlake: Skip Gpio configuration from FSP
......................................................................

Patch Set 1:

(3 comments)

https://review.coreboot.org/c/coreboot/+/44913/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/44913/1//COMMIT_MSG@7 
PS1, Line 7: Gpio
nit: GPIO

https://review.coreboot.org/c/coreboot/+/44913/1//COMMIT_MSG@9 
PS1, Line 9: v3333
Do you need to add Cq-Depend on chromium CL? Or is FSP already upreved to v3333+?

https://review.coreboot.org/c/coreboot/+/44913/1//COMMIT_MSG@10 
PS1, Line 10: Coreboot
Verify that the word 'coreboot' is lowercase (lint-stable-021-coreboot-lowercase): 'coreboot' should be lowercase in commit message
test failed

Change in coreboot[master]: soc/intel/tigerlake: Skip GPIO configuration from FSP

[Srinidhi N Kaushik (Code Review)]

Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Dossym Nurmukhanov, Nick Vaccaro, Raj Astekar, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/44913

to look at the new patch set (#2).

Change subject: soc/intel/tigerlake: Skip GPIO configuration from FSP
......................................................................

soc/intel/tigerlake: Skip GPIO configuration from FSP

FSP v3333 or later, provides a new UPD to Skip configuring
GPIO settings from FSP. coreboot should provide all the
required GPIO configuration for the platform when this UPD
is set.

BUG=b:166790597, 146390704
BRANCH=none
TEST=build and boot volteer proto2

Signed-off-by: Srinidhi N Kaushik 
Change-Id: If32f35a188d510db8e4d8973cae78297d49a9240
---
M src/soc/intel/tigerlake/romstage/fsp_params.c
1 file changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/44913/2

Change in coreboot[master]: soc/intel/tigerlake: Skip GPIO configuration from FSP

[Srinidhi N Kaushik (Code Review)]

Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44913 )

Change subject: soc/intel/tigerlake: Skip GPIO configuration from FSP
......................................................................

Patch Set 2:

(3 comments)

https://review.coreboot.org/c/coreboot/+/44913/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/44913/1//COMMIT_MSG@7 
PS1, Line 7: Gpio
> nit: GPIO

Done

https://review.coreboot.org/c/coreboot/+/44913/1//COMMIT_MSG@9 
PS1, Line 9: v3333
> Do you need to add Cq-Depend on chromium CL? Or is FSP already upreved to v3333+?

Chromium CL is not ready yet, will add it once there is a merge CL for v3333.

https://review.coreboot.org/c/coreboot/+/44913/1//COMMIT_MSG@10 
PS1, Line 10: Coreboot
> Verify that the word 'coreboot' is lowercase (lint-stable-021-coreboot-lowercase): 'coreboot' should […]

Done

Change in coreboot[master]: soc/intel/tigerlake: Skip GPIO configuration from FSP

[Dossym Nurmukhanov (Code Review)]

Dossym Nurmukhanov has uploaded a new patch set (#3) to the change originally created by Srinidhi N Kaushik. ( https://review.coreboot.org/c/coreboot/+/44913 )

Change subject: soc/intel/tigerlake: Skip GPIO configuration from FSP
......................................................................

soc/intel/tigerlake: Skip GPIO configuration from FSP

FSP v3333 or later, provides a new UPD to Skip configuring
GPIO settings from FSP. coreboot should provide all the
required GPIO configuration for the platform when this UPD
is set.

BUG=b:166790597, 146390704
BRANCH=none
TEST=build and boot volteer proto2

Cq-Depend:chromium-internal:3240396,chromium-internal:2870145
Signed-off-by: Srinidhi N Kaushik 
Change-Id: If32f35a188d510db8e4d8973cae78297d49a9240
---
M src/soc/intel/tigerlake/romstage/fsp_params.c
1 file changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/44913/3

Change in coreboot[master]: soc/intel/tigerlake: Skip GPIO configuration from FSP

[Dossym Nurmukhanov (Code Review)]

Dossym Nurmukhanov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44913 )

Change subject: soc/intel/tigerlake: Skip GPIO configuration from FSP
......................................................................

Patch Set 3:

(1 comment)

Updated Cq-Depend for this CL

https://review.coreboot.org/c/coreboot/+/44913/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/44913/1//COMMIT_MSG@9 
PS1, Line 9: v3333
> Chromium CL is not ready yet, will add it once there is a merge CL for v3333.

Done

Change in coreboot[master]: soc/intel/tigerlake: Skip GPIO configuration from FSP

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44913 )

Change subject: soc/intel/tigerlake: Skip GPIO configuration from FSP
......................................................................

Patch Set 3: Code-Review+2

Change in coreboot[master]: soc/intel/tigerlake: Skip GPIO configuration from FSP

[Dossym Nurmukhanov (Code Review)]

Dossym Nurmukhanov has uploaded a new patch set (#4) to the change originally created by Srinidhi N Kaushik. ( https://review.coreboot.org/c/coreboot/+/44913 )

Change subject: soc/intel/tigerlake: Skip GPIO configuration from FSP
......................................................................

soc/intel/tigerlake: Skip GPIO configuration from FSP

FSP v3333 or later, provides a new UPD to Skip configuring
GPIO settings from FSP. coreboot should provide all the
required GPIO configuration for the platform when this UPD
is set.

BUG=b:166790597, b:146390704
BRANCH=none
TEST=build and boot volteer proto2

Cq-Depend:chromium-internal:3240396,chromium-internal:2870145
Signed-off-by: Srinidhi N Kaushik 
Change-Id: If32f35a188d510db8e4d8973cae78297d49a9240
---
M src/soc/intel/tigerlake/romstage/fsp_params.c
1 file changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/44913/4

Change in coreboot[master]: soc/intel/tigerlake: Skip GPIO configuration from FSP

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44913 )

Change subject: soc/intel/tigerlake: Skip GPIO configuration from FSP
......................................................................

soc/intel/tigerlake: Skip GPIO configuration from FSP

FSP v3333 or later, provides a new UPD to Skip configuring
GPIO settings from FSP. coreboot should provide all the
required GPIO configuration for the platform when this UPD
is set.

BUG=b:166790597, b:146390704
BRANCH=none
TEST=build and boot volteer proto2

Cq-Depend:chromium-internal:3240396,chromium-internal:2870145
Signed-off-by: Srinidhi N Kaushik 
Change-Id: If32f35a188d510db8e4d8973cae78297d49a9240
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44913
Reviewed-by: Furquan Shaikh 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/tigerlake/romstage/fsp_params.c
1 file changed, 3 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Srinidhi N Kaushik: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c
index 2ba276d..4b68cb6 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params.c
@@ -87,6 +87,9 @@
    dev = pcidev_path_on_root(PCH_DEVFN_ISH);
    m_cfg->PchIshEnable = is_dev_enabled(dev);

+	/* Skip GPIO configuration from FSP */
+	m_cfg->GpioOverride = 0x1;
+
    /* DP port config */
    m_cfg->DdiPortAConfig = config->DdiPortAConfig;
    m_cfg->DdiPortBConfig = config->DdiPortBConfig;