Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52742 )
Change subject: cpu/x86/smm: increase SMM_CODE_SEGMENT_SIZE ......................................................................
cpu/x86/smm: increase SMM_CODE_SEGMENT_SIZE
Increase SMM_CODE_SEGMENT_SIZE to 0x10f00 to accomodate for the permanent SMM handler's size on tiger lake.
BUG=b:186661594 TEST=`emerge-volteer coreboot chromeos-bootimage`, flash voxel and verify it boots to kernel.
Change-Id: Ie9fdae7cdf812d92a4d3b61368de884f4e55aa3a Signed-off-by: Nick Vaccaro nvaccaro@google.com --- M src/cpu/x86/smm/smm_module_loader.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/52742/1
diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index e3b8417..2e046f3 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -10,7 +10,7 @@ #include <security/intel/stm/SmmStm.h>
#define FXSAVE_SIZE 512 -#define SMM_CODE_SEGMENT_SIZE 0x10000 +#define SMM_CODE_SEGMENT_SIZE 0x10f00 /* FXSAVE area during relocation. While it may not be strictly needed the SMM stub code relies on the FXSAVE area being non-zero to enable SSE instructions within SMM mode. */