Change in coreboot[master]: soc/intel/tigerlake: Add FSP UPDs for minimum assertion widths - coreboot-gerrit

19 Aug 2020


      Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44557 )
Change subject: soc/intel/tigerlake: Add FSP UPDs for minimum assertion widths
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Patch Set 1: Code-Review+1
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I8180d95a2185c3786334e10613f47e77b7bc9d5f
Gerrit-Change-Number: 44557
Gerrit-PatchSet: 1
Gerrit-Owner: Jamie Ryu jamie.m.ryu@intel.com
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
Gerrit-Reviewer: Raj Astekar raj.astekar@intel.com
Gerrit-Reviewer: Rizwan Qureshi rizwan.qureshi@intel.com
Gerrit-Reviewer: Sridhar Siricilla sridhar.siricilla@intel.com
Gerrit-Reviewer: V Sowmya v.sowmya@intel.com
Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com
Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org
Gerrit-Comment-Date: Wed, 19 Aug 2020 07:49:43 +0000
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