Attention is currently required from: Nico Huber, Ethan Tsao, Ravishankar Sarawadi, Tim Wawrzynczak, Paul Menzel, Raj Astekar, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61389 )
Change subject: soc/intel/graphics: Create Kconfig for mapping graphic memory base ......................................................................
Patch Set 19:
(2 comments)
File src/soc/intel/common/block/graphics/Kconfig:
https://review.coreboot.org/c/coreboot/+/61389/comment/c9184899_893f34e1 PS19, Line 26: to : reach at DSM
In future platform, GMADR is replaced by LMEMBAR which is fixed map to DSM/GSM. There is document 643504(FAS) mention it.
GTT size is "fixed" at 8MB(which it is WIP to update in external document).
@Ethan, Please correct me, I don't think this code adjustment is due to FSP GFX PEIM. I read this as HW change ?
https://review.coreboot.org/c/coreboot/+/61389/comment/04c55a09_33d42d76 PS19, Line 29: GTT_SIZE
Yes, the hardware process behind BAR 2(0x18) is changed in future platform. […]
Adding to what Nico had mentioned. This is my understanding with future Intel SoC platform design change
1. GTTMMADR (used for pointing to the GTT base) aka BAR0 remains unchanged. 2. GMADR (used to point at DSM base) aka BAR2 is now renamed to LMEMBAR0 and pointing to the GTT base hence, we need to add GTT size to reach at DSM base using graphics_get_memory_base(). For older SoC platforms where GMADR already points to the DSM, we don't need any additional math but for future SOC, we need that offset adjustment which is nothing but GTT size.