[M] Change in coreboot[main]: cpu/x86/mtrr: Use fls/ffs from lib.h

[Shuo Liu (Code Review)]

Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85104?usp=email )

Change subject: cpu/x86/mtrr: Use fls/ffs from lib.h
......................................................................

cpu/x86/mtrr: Use fls/ffs from lib.h

fls/ff(m)s definitions from lib.h and cpu/x86/mtrr.h are
duplicated. Use lib.h definition which is more generic.

Change-Id: Ic9c6f1027447b04627d7f21d777cbea142588093
Signed-off-by: Shuo Liu 
Suggested-by: Angel Pons 
---
M src/cpu/x86/mtrr/earlymtrr.c
M src/cpu/x86/mtrr/mtrr.c
M src/include/cpu/x86/mtrr.h
M src/soc/amd/common/block/pci/amd_pci_mmconf.c
4 files changed, 11 insertions(+), 59 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/85104/1

diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c
index a55b2dc..c62326e 100644
--- a/src/cpu/x86/mtrr/earlymtrr.c
+++ b/src/cpu/x86/mtrr/earlymtrr.c
@@ -94,8 +94,8 @@
    		return -1;
    	}

-		addr_lsb = fls(addr);
-		size_msb = fms(size);
+		addr_lsb = __fls(addr);
+		size_msb = __ffs(size);

/* All MTRR entries need to have their base aligned to the mask
    	   size. The maximum size is calculated by a function of the
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index 5c42eb9..b9fe9f9 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -20,6 +20,7 @@
 #include <cpu/x86/mtrr.h>
 #include <device/device.h>
 #include <device/pci_ids.h>
+#include <lib.h>
 #include <memrange.h>
 #include <string.h>
 #include <types.h>
@@ -427,19 +428,6 @@
    regs->mask.hi = rsize >> 32;
 }

-/*
- * fms64: find most significant bit set in a 64-bit word
- * As samples, fms64(0x0) = 0; fms64(0x4400) = 14;
- * fms64(0x40400000000) = 42.
- */
-static uint32_t fms64(uint64_t x)
-{
-	uint32_t hi = (uint32_t)(x >> 32);
-	if (!hi)
-		return fms((uint32_t)x);
-	return fms(hi) + 32;
-}
-
 static void calc_var_mtrr_range(struct var_mtrr_state *var_state,
    			uint64_t base, uint64_t size, int mtrr_type)
 {
@@ -448,8 +436,8 @@
    	uint32_t size_msb;
    	uint64_t mtrr_size;

-		addr_lsb = fls64(base);
-		size_msb = fms64(size);
+		addr_lsb = __fls64(base);
+		size_msb = __ffs64(size);

/* All MTRR entries need to have their base aligned to the mask
    	 * size. The maximum size is calculated by a function of the
@@ -502,7 +490,7 @@
    best_count = var_state.mtrr_index;
    var_state.mtrr_index = 0;

-	for (align = fls(hole) + 1; align <= fms(hole); ++align) {
+	for (align = __fls(hole) + 1; align <= __ffs(hole); ++align) {
    	const uint64_t hole_end = ALIGN_UP((uint64_t)hole, 1 << align);
    	if (hole_end > limit)
    		break;
@@ -594,7 +582,7 @@
    	 */
    	next = memranges_next_entry(var_state->addr_space, r);
    	if (next == NULL) {
-			b2_limit = ALIGN_UP((uint64_t)b1, 1 << fms(b1));
+			b2_limit = ALIGN_UP((uint64_t)b1, 1 << __ffs(b1));
    		/* If it's the last range above 4GiB, we won't carve
    		   the hole out. If an OS wanted to move MMIO there,
    		   it would have to override the MTRR setting using
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index c20d573..efc48fe 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -77,6 +77,7 @@

#include <stdint.h>
 #include <stddef.h>
+#include <lib.h>

/*
  * The MTRR code has some side effects that the callers should be aware for.
@@ -144,47 +145,9 @@
 void commit_mtrr_setup(const struct var_mtrr_context *ctx);
 void postcar_mtrr_setup(void);

-/* fms: find most significant bit set, stolen from Linux Kernel Source. */
-static inline unsigned int fms(unsigned int x)
-{
-	unsigned int r;
-
-	__asm__("bsrl %1,%0\n\t"
-		"jnz 1f\n\t"
-		"movl $0,%0\n"
-		"1:" : "=r" (r) : "mr" (x));
-	return r;
-}
-
-/* fls: find least significant bit set */
-static inline unsigned int fls(unsigned int x)
-{
-	unsigned int r;
-
-	__asm__("bsfl %1,%0\n\t"
-		"jnz 1f\n\t"
-		"movl $32,%0\n"
-		"1:" : "=r" (r) : "mr" (x));
-	return r;
-}
-
-/*
- * fls64: find least significant bit set in a 64-bit word
- * As samples, fls64(0x0) = 64; fls64(0x4400) = 10;
- * fls64(0x40400000000) = 34.
- */
-static uint32_t fls64(uint64_t x)
-{
-	uint32_t lo = (uint32_t)x;
-	if (lo)
-		return fls(lo);
-	uint32_t hi = x >> 32;
-	return fls(hi) + 32;
-}
-
 static inline uint64_t calculate_var_mtrr_size(uint64_t mask)
 {
-	return 1 << (fls64(mask >> RANGE_SHIFT) + RANGE_SHIFT);
+	return 1 << (__fls64(mask >> RANGE_SHIFT) + RANGE_SHIFT);
 }

#endif /* !defined(__ASSEMBLER__) */
diff --git a/src/soc/amd/common/block/pci/amd_pci_mmconf.c b/src/soc/amd/common/block/pci/amd_pci_mmconf.c
index fb4db39..251ceb2 100644
--- a/src/soc/amd/common/block/pci/amd_pci_mmconf.c
+++ b/src/soc/amd/common/block/pci/amd_pci_mmconf.c
@@ -4,6 +4,7 @@
 #include <cpu/amd/msr.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
+#include <lib.h>

void enable_pci_mmconf(void)
 {
@@ -11,6 +12,6 @@

mmconf.hi = 0;
    mmconf.lo = CONFIG_ECAM_MMCONF_BASE_ADDRESS | MMIO_RANGE_EN
-			| fms(CONFIG_ECAM_MMCONF_BUS_NUMBER) << MMIO_BUS_RANGE_SHIFT;
+			| __ffs(CONFIG_ECAM_MMCONF_BUS_NUMBER) << MMIO_BUS_RANGE_SHIFT;
    wrmsr(MMIO_CONF_BASE, mmconf);
 }