Change in coreboot[master]: nb/intel/x4x/raminit: Support programming DDR3 timings

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded a new change for review. ( https://review.coreboot.org/19873 )

Change subject: nb/intel/x4x/raminit: Support programming DDR3 timings
......................................................................

nb/intel/x4x/raminit: Support programming DDR3 timings

Change-Id: Ia2494684ec66d84d4dc27c6a6b425a33ace6e827
Signed-off-by: Arthur Heymans 
---
M src/northbridge/intel/x4x/raminit_ddr23.c
1 file changed, 74 insertions(+), 35 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/19873/1

diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c
index fc8e5a0..4db29f5 100644
--- a/src/northbridge/intel/x4x/raminit_ddr23.c
+++ b/src/northbridge/intel/x4x/raminit_ddr23.c
@@ -496,15 +496,77 @@
    	5200
    };

-	ta1 = 6;
-	ta2 = 6;
-	ta3 = 5;
-	ta4 = 8;
+	const static u8 ddr3_turnaround_tab[3][6][4] = {
+		{ /* DDR3 800 */
+			{0x7, 0x7, 0x9,	0x9},	/* CL = 5 */
+			{0x7, 0x8, 0x8,	0x9},	/* CL = 6 */
+		},
+		{ /* DDR3 1066 */
+			{0x0, 0x0, 0x0, 0x0},	/* CL = 5 - Not supported */
+			{0x7, 0x7, 0x9,	0x9},	/* CL = 6 */
+			{0x7, 0x8, 0x8,	0x9},	/* CL = 7 */
+			{0x7, 0x9, 0x7,	0x9}	/* CL = 8 */
+		},
+		{ /* DDR3 1333 */
+			{0x0, 0x0, 0x0,	0x0},	/* CL = 5 - Not supported */
+			{0x0, 0x0, 0x0, 0x0},	/* CL = 6 - Not supported */
+			{0x0, 0x0, 0x0,	0x0},	/* CL = 7 - Not supported */
+			{0x7, 0x9, 0x8,	0x9},	/* CL = 8 */
+			{0x7, 0xA, 0x7, 0x9},	/* CL = 9 */
+			{0x7, 0xB, 0x6,	0x9},	/* CL = 10 */
+		}
+	};

-	twl = s->selected_timings.CAS - 1;
+	/* [DDR freq][0x26F & 1][pagemod] */
+	const static u8 ddr2_x252_tab[2][2][2] =  {
+		{ /* DDR2 667 */
+			{12, 16},
+			{14, 18}
+		},
+		{ /* DDR2 800 */
+			{14, 18},
+			{16, 20}
+		}
+	};
+
+	const static u8 ddr3_x252_tab[3][2][2] =  {
+		{ /* DDR3 800 */
+			{16, 20},
+			{18, 22}
+		},
+		{ /* DDR3 1067 */
+			{20, 26},
+			{26, 26}
+		},
+		{ /* DDR3 1333 */
+			{20, 30},
+			{22, 32},
+		}
+	};
+
+	if (s->spd_type == DDR2) {
+		ta1 = 6;
+		ta2 = 6;
+		ta3 = 5;
+		ta4 = 8;
+	} else {
+		ta1 = ddr3_turnaround_tab[s->selected_timings.mem_clk - MEM_CLOCK_800MHz]
+			[s->selected_timings.CAS - 5][3];
+		ta2 = ddr3_turnaround_tab[s->selected_timings.mem_clk - MEM_CLOCK_800MHz]
+			[s->selected_timings.CAS - 5][0];
+		ta3 = ddr3_turnaround_tab[s->selected_timings.mem_clk - MEM_CLOCK_800MHz]
+			[s->selected_timings.CAS - 5][1];
+		ta4 = ddr3_turnaround_tab[s->selected_timings.mem_clk - MEM_CLOCK_800MHz]
+			[s->selected_timings.CAS - 5][2];
+	}
+
+	if (s->spd_type == DDR2)
+		twl = s->selected_timings.CAS - 1;
+	else /* DDR3 */
+		twl = s->selected_timings.mem_clk - MEM_CLOCK_800MHz + 5;

FOR_EACH_POPULATED_DIMM(s->dimms, i) {
-		if (s->dimms[i].n_banks == 1) {
+		if (s->dimms[i].n_banks == 1) { /* 8 banks */
    		trpmod = 1;
    		bankmod = 0;
    	}
@@ -534,35 +596,12 @@
    		s->selected_timings.tRFC;
    	reg8 = (MCHBAR8(0x400*i + 0x26f) >> 1) & 1;
    	if (bankmod) {
-			switch (s->selected_timings.mem_clk) {
-			default:
-			case MEM_CLOCK_667MHz:
-				if (reg8) {
-					if (pagemod)
-						reg32 |= 16 << 22;
-					else
-						reg32 |= 12 << 22;
-				} else {
-					if (pagemod)
-						reg32 |= 18 << 22;
-					else
-						reg32 |= 14 << 22;
-				}
-				break;
-			case MEM_CLOCK_800MHz:
-				if (reg8) {
-					if (pagemod)
-						reg32 |= 18 << 22;
-					else
-						reg32 |= 14 << 22;
-				} else {
-					if (pagemod)
-						reg32 |= 20 << 22;
-					else
-						reg32 |= 16 << 22;
-				}
-				break;
-			}
+			if (s->spd_type == DDR2)
+				reg32 |= ddr2_x252_tab[s->selected_timings.mem_clk - MEM_CLOCK_667MHz]
+					[reg8][pagemod] << 22;
+			else
+				reg32 |= ddr3_x252_tab[s->selected_timings.mem_clk - MEM_CLOCK_800MHz]
+					[reg8][pagemod] << 22;
    	}
    	MCHBAR32(0x400*i + 0x252) = reg32;