HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31107
Change subject: nb/intel/i945: Remove stuff done at bootblock ......................................................................
nb/intel/i945: Remove stuff done at bootblock
Upper 128bytes of CMOS and RCBA are already enabled at bootblock.
Change-Id: I3f34380b0e700cf60688ad58465f9cb0aeda0928 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/i945/raminit.c 2 files changed, 0 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/31107/1
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index cc7b1ef..81874ab 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -157,7 +157,6 @@
/* Setting up Southbridge. In the northbridge code. */ printk(BIOS_DEBUG, "Setting up static southbridge registers..."); - pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);
pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, 0x80); /* ACPI_CNTL: Enable ACPI BAR */ @@ -174,9 +173,6 @@ outw((1 << 1), DEFAULT_PMBASE | 0x60 | 0x06); /* clear 2nd timeout */ printk(BIOS_DEBUG, " done.\n");
- /* Enable upper 128bytes of CMOS */ - RCBA32(RC) = (1 << 2); - printk(BIOS_DEBUG, "Setting up static northbridge registers..."); /* Set up all hardcoded northbridge BARs */ pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 64c87da..f3c3df6 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -2414,9 +2414,6 @@ { MCHBAR32(REPC) |= (1 << 0);
- /* enable upper CMOS */ - RCBA32(0x3400) = (1 << 2); - /* Program Receive Enable Timings */ if (sysinfo->boot_path == BOOT_PATH_RESUME) { sdram_recover_receive_enable();
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31107 )
Change subject: nb/intel/i945: Remove stuff done at bootblock ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/#/c/31107/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31107/1//COMMIT_MSG@7 PS1, Line 7: nb/intel/i945: Remove stuff done at bootblock This is too ambiguous, sounds like you are removing code from bootblock.
https://review.coreboot.org/#/c/31107/1//COMMIT_MSG@10 PS1, Line 10: Please test, including resuming from suspend.
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31107
to look at the new patch set (#2).
Change subject: nb/intel/i945: No need to redo stuff already done at bootblock ......................................................................
nb/intel/i945: No need to redo stuff already done at bootblock
Upper 128bytes of CMOS and RCBA are already enabled at bootblock. Tested on 945g-MA. Resuming from suspend is working fine
Change-Id: I3f34380b0e700cf60688ad58465f9cb0aeda0928 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/i945/raminit.c 2 files changed, 0 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/31107/2
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31107 )
Change subject: nb/intel/i945: No need to redo stuff already done at bootblock ......................................................................
Patch Set 2: Code-Review+2
(1 comment)
https://review.coreboot.org/#/c/31107/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31107/2//COMMIT_MSG@7 PS2, Line 7: nb/intel/i945: No need to redo stuff already done at bootblock This should be a statement about the change not the issue. e.g.
Remove initialization already done at bootblock
Hello Patrick Rudolph, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31107
to look at the new patch set (#3).
Change subject: nb/intel/i945: Remove initialization already done at bootblock ......................................................................
nb/intel/i945: Remove initialization already done at bootblock
Upper 128bytes of CMOS and RCBA are already enabled at bootblock. Tested on 945g-MA. Resuming from suspend is working fine
Change-Id: I3f34380b0e700cf60688ad58465f9cb0aeda0928 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/i945/raminit.c 2 files changed, 0 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/31107/3
Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31107 )
Change subject: nb/intel/i945: Remove initialization already done at bootblock ......................................................................
nb/intel/i945: Remove initialization already done at bootblock
Upper 128bytes of CMOS and RCBA are already enabled at bootblock. Tested on 945g-MA. Resuming from suspend is working fine
Change-Id: I3f34380b0e700cf60688ad58465f9cb0aeda0928 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/31107 Reviewed-by: Nico Huber nico.h@gmx.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/i945/raminit.c 2 files changed, 0 insertions(+), 7 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index be882de..763300a 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -157,7 +157,6 @@
/* Setting up Southbridge. In the northbridge code. */ printk(BIOS_DEBUG, "Setting up static southbridge registers..."); - pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);
pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, 0x80); /* ACPI_CNTL: Enable ACPI BAR */ @@ -174,9 +173,6 @@ outw((1 << 1), DEFAULT_PMBASE | 0x60 | 0x06); /* clear 2nd timeout */ printk(BIOS_DEBUG, " done.\n");
- /* Enable upper 128bytes of CMOS */ - RCBA32(RC) = (1 << 2); - printk(BIOS_DEBUG, "Setting up static northbridge registers..."); /* Set up all hardcoded northbridge BARs */ pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 64c87da..f3c3df6 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -2414,9 +2414,6 @@ { MCHBAR32(REPC) |= (1 << 0);
- /* enable upper CMOS */ - RCBA32(0x3400) = (1 << 2); - /* Program Receive Enable Timings */ if (sysinfo->boot_path == BOOT_PATH_RESUME) { sdram_recover_receive_enable();
-
HAOUAS Elyes (Code Review) -
Nico Huber (Code Review)