Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41941 )
Change subject: soc/intel/broadwell: Move chip.h to northbridge ......................................................................
soc/intel/broadwell: Move chip.h to northbridge
We need to update the name of the config struct to make sconfig happy, but this means the resulting binaries are no longer reproducible...
But now, soc/intel/broadwell is finally no more. Now we need to clean up the mess that was left after scattering everything into three parts...
Change-Id: I199cddb05de460359d1fade21e6171a218377f47 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/google/auron/devicetree.cb M src/mainboard/google/auron/variants/auron_paine/overridetree.cb M src/mainboard/google/auron/variants/auron_yuna/overridetree.cb M src/mainboard/google/auron/variants/buddy/overridetree.cb M src/mainboard/google/auron/variants/gandof/overridetree.cb M src/mainboard/google/auron/variants/lulu/overridetree.cb M src/mainboard/google/auron/variants/samus/overridetree.cb M src/mainboard/google/jecht/devicetree.cb M src/mainboard/intel/wtm2/devicetree.cb M src/mainboard/purism/librem_bdw/devicetree.cb M src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb M src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb R src/northbridge/intel/broadwell/chip.h M src/northbridge/intel/broadwell/igd.c M src/southbridge/intel/wildcatpoint/soc_chip.h 15 files changed, 16 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/41941/1
diff --git a/src/mainboard/google/auron/devicetree.cb b/src/mainboard/google/auron/devicetree.cb index a84aa98..4bcf672 100644 --- a/src/mainboard/google/auron/devicetree.cb +++ b/src/mainboard/google/auron/devicetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/broadwell +chip northbridge/intel/broadwell
# IGD Displays register "gfx" = "GMA_STATIC_DISPLAYS(0)" diff --git a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb index 70b1ebd..a53a060 100644 --- a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb +++ b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/broadwell +chip northbridge/intel/broadwell
# Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb index 67b9131..ed33680 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb +++ b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/broadwell +chip northbridge/intel/broadwell
# Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb index f814280..e04744d 100644 --- a/src/mainboard/google/auron/variants/buddy/overridetree.cb +++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/broadwell +chip northbridge/intel/broadwell
# Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/google/auron/variants/gandof/overridetree.cb b/src/mainboard/google/auron/variants/gandof/overridetree.cb index e35d3a5..6236e43 100644 --- a/src/mainboard/google/auron/variants/gandof/overridetree.cb +++ b/src/mainboard/google/auron/variants/gandof/overridetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/broadwell +chip northbridge/intel/broadwell
# Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/google/auron/variants/lulu/overridetree.cb b/src/mainboard/google/auron/variants/lulu/overridetree.cb index 70b1ebd..a53a060 100644 --- a/src/mainboard/google/auron/variants/lulu/overridetree.cb +++ b/src/mainboard/google/auron/variants/lulu/overridetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/broadwell +chip northbridge/intel/broadwell
# Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb index 93e96ca..dd61c18 100644 --- a/src/mainboard/google/auron/variants/samus/overridetree.cb +++ b/src/mainboard/google/auron/variants/samus/overridetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/broadwell +chip northbridge/intel/broadwell
# Enable DDI2 Hotplug with 6ms pulse register "gpu_dp_c_hotplug" = "0x06" diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb index 19d0c48..bb8df2d 100644 --- a/src/mainboard/google/jecht/devicetree.cb +++ b/src/mainboard/google/jecht/devicetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/broadwell +chip northbridge/intel/broadwell
# Disable eDP Hotplug register "gpu_dp_d_hotplug" = "0x00" diff --git a/src/mainboard/intel/wtm2/devicetree.cb b/src/mainboard/intel/wtm2/devicetree.cb index 8d36f04..3b79ea3 100644 --- a/src/mainboard/intel/wtm2/devicetree.cb +++ b/src/mainboard/intel/wtm2/devicetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/broadwell +chip northbridge/intel/broadwell
# Enable DisplayPort 1 Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/purism/librem_bdw/devicetree.cb b/src/mainboard/purism/librem_bdw/devicetree.cb index 13b9e5e..543570e 100644 --- a/src/mainboard/purism/librem_bdw/devicetree.cb +++ b/src/mainboard/purism/librem_bdw/devicetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/broadwell +chip northbridge/intel/broadwell
# Enable eDP Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb b/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb index d3d0ae7..11ae807 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb +++ b/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/broadwell +chip northbridge/intel/broadwell
# Port 0 is HDD # Port 3 is M.2 NGFF diff --git a/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb b/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb index c0c8d03..d526ac7 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb +++ b/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/broadwell +chip northbridge/intel/broadwell
# Port 0 is HDD # Port 1 is M.2 NGFF diff --git a/src/soc/intel/broadwell/chip.h b/src/northbridge/intel/broadwell/chip.h similarity index 96% rename from src/soc/intel/broadwell/chip.h rename to src/northbridge/intel/broadwell/chip.h index 45f91d8..9a62630 100644 --- a/src/soc/intel/broadwell/chip.h +++ b/src/northbridge/intel/broadwell/chip.h @@ -7,7 +7,7 @@ #include <intelblocks/cfg.h> #include <stdint.h>
-struct soc_intel_broadwell_config { +struct northbridge_intel_broadwell_config { /* * Interrupt Routing configuration * If bit7 is 1, the interrupt is disabled. @@ -155,6 +155,6 @@ int tcc_offset; };
-typedef struct soc_intel_broadwell_config config_t; +typedef struct northbridge_intel_broadwell_config config_t;
#endif diff --git a/src/northbridge/intel/broadwell/igd.c b/src/northbridge/intel/broadwell/igd.c index 6c0da56..b032782 100644 --- a/src/northbridge/intel/broadwell/igd.c +++ b/src/northbridge/intel/broadwell/igd.c @@ -575,7 +575,7 @@
static void gma_generate_ssdt(const struct device *dev) { - const struct soc_intel_broadwell_config *chip = dev->chip_info; + const struct northbridge_intel_broadwell_config *chip = dev->chip_info;
drivers_intel_gma_displays_ssdt_generate(&chip->gfx); } diff --git a/src/southbridge/intel/wildcatpoint/soc_chip.h b/src/southbridge/intel/wildcatpoint/soc_chip.h index c59f562..4f8d4af 100644 --- a/src/southbridge/intel/wildcatpoint/soc_chip.h +++ b/src/southbridge/intel/wildcatpoint/soc_chip.h @@ -3,6 +3,6 @@ #ifndef _SOC_BROADWELL_SOC_CHIP_H_ #define _SOC_BROADWELL_SOC_CHIP_H_
-#include <soc/intel/broadwell/chip.h> +#include <northbridge/intel/broadwell/chip.h>
#endif /* _SOC_BROADWELL_SOC_CHIP_H_ */
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41941
to look at the new patch set (#9).
Change subject: soc/intel/broadwell: Move chip.h to northbridge ......................................................................
soc/intel/broadwell: Move chip.h to northbridge
We need to update the name of the config struct to make sconfig happy, but this means the resulting binaries are no longer reproducible...
But now, soc/intel/broadwell is finally no more. Now we need to clean up the mess that was left after scattering everything into three parts...
Change-Id: I199cddb05de460359d1fade21e6171a218377f47 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/google/auron/devicetree.cb M src/mainboard/google/auron/variants/auron_paine/overridetree.cb M src/mainboard/google/auron/variants/auron_yuna/overridetree.cb M src/mainboard/google/auron/variants/buddy/overridetree.cb M src/mainboard/google/auron/variants/gandof/overridetree.cb M src/mainboard/google/auron/variants/lulu/overridetree.cb M src/mainboard/google/auron/variants/samus/overridetree.cb M src/mainboard/google/jecht/devicetree.cb M src/mainboard/intel/wtm2/devicetree.cb M src/mainboard/purism/librem_bdw/devicetree.cb M src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb M src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb R src/northbridge/intel/broadwell/chip.h M src/northbridge/intel/broadwell/igd.c M src/southbridge/intel/wildcatpoint/soc_chip.h 15 files changed, 16 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/41941/9
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41941
to look at the new patch set (#12).
Change subject: soc/intel/broadwell: Move chip.h to northbridge ......................................................................
soc/intel/broadwell: Move chip.h to northbridge
We need to update the name of the config struct to make sconfig happy, but this means the resulting binaries are no longer reproducible...
But now, soc/intel/broadwell is finally no more. Now we need to clean up the mess that was left after scattering everything into three parts...
Change-Id: I199cddb05de460359d1fade21e6171a218377f47 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/google/auron/devicetree.cb M src/mainboard/google/auron/variants/auron_paine/overridetree.cb M src/mainboard/google/auron/variants/auron_yuna/overridetree.cb M src/mainboard/google/auron/variants/buddy/overridetree.cb M src/mainboard/google/auron/variants/gandof/overridetree.cb M src/mainboard/google/auron/variants/lulu/overridetree.cb M src/mainboard/google/auron/variants/samus/overridetree.cb M src/mainboard/google/jecht/devicetree.cb M src/mainboard/intel/wtm2/devicetree.cb M src/mainboard/purism/librem_bdw/devicetree.cb M src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb M src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb R src/northbridge/intel/broadwell/chip.h M src/northbridge/intel/broadwell/igd.c M src/southbridge/intel/wildcatpoint/soc_chip.h 15 files changed, 16 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/41941/12
Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/41941 )
Change subject: soc/intel/broadwell: Move chip.h to northbridge ......................................................................
Abandoned
-
Angel Pons (Code Review)