Patch set updated for coreboot: nb/amd/mct_ddr3: Scale lane delays for each DIMM after MEMCLK change

[Timothy Pearson]

Timothy Pearson ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14479

-gerrit

commit f8060223dd6a70f7bd3dad8be36cfbb46909acb4
Author: Timothy Pearson 
Date:   Fri Apr 22 22:16:45 2016 -0500

nb/amd/mct_ddr3: Scale lane delays for each DIMM after MEMCLK change

When more than one DIMM is installed on a DCT, only the first DIMM
    delay values are scaled to the new memory clock frequency after a
    memory clock change during write leveling.

Store the previous memory clock of each DIMM during write leveling
    to ensure that every DIMM has its delay values rescaled.

Change-Id: I56e816d3d3256925598219d92783246f5f4ab567
    Signed-off-by: Timothy Pearson 
---
 src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 4 ++--
 src/northbridge/amd/amdmct/mct_ddr3/mwlc_d.h  | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
index 9702126..6e1c850 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
@@ -1212,7 +1212,7 @@ void procConfig(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, ui
    					((pDCTData->WLGrossDelayPrevPass[lane_count*dimm+ByteLane] & 0x1f) << 5);
    				SeedTotalPreScaling[ByteLane] = (SeedTotal[ByteLane] - RegisterDelay - (0x20 * WrDqDqsEarly));
    				SeedTotal[ByteLane] = (int32_t) (RegisterDelay + ((((int64_t) SeedTotalPreScaling[ByteLane]) *
-						fam15h_freq_tab[MemClkFreq] * 100) / (fam15h_freq_tab[pDCTData->WLPrevMemclkFreq] * 100)));
+						fam15h_freq_tab[MemClkFreq] * 100) / (fam15h_freq_tab[pDCTData->WLPrevMemclkFreq[dimm]] * 100)));
    			}

/* Generate register values from seeds */
@@ -1326,7 +1326,7 @@ void procConfig(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, ui
    	}
    }

-	pDCTData->WLPrevMemclkFreq = MemClkFreq;
+	pDCTData->WLPrevMemclkFreq[dimm] = MemClkFreq;
    setWLByteDelay(pDCTstat, dct, ByteLane, dimm, 0, pass, lane_count);
 }

diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mwlc_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mwlc_d.h
index 28359a1..ca04d28 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mwlc_d.h
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mwlc_d.h
@@ -145,7 +145,7 @@ typedef struct _sDCTStruct
    int32_t WLCriticalGrossDelayFirstPass;
    int32_t WLCriticalGrossDelayPrevPass;
    int32_t WLCriticalGrossDelayFinalPass;
-	uint16_t WLPrevMemclkFreq;
+	uint16_t WLPrevMemclkFreq[MAX_TOTAL_DIMMS];
    u16 RegMan1Present;
    u8 DimmPresent[MAX_TOTAL_DIMMS];/* Indicates which DIMMs are present */
    				/* from Total Number of DIMMs(per Node)*/