Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36381 )
Change subject: mb/asrock/h110m: use SuperIO acpigen ......................................................................
mb/asrock/h110m: use SuperIO acpigen
Change-Id: I57b67d10968e5e035536bcb0d8329ce09d50194b Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/asrock/h110m/acpi/superio.asl M src/mainboard/asrock/h110m/devicetree.cb 2 files changed, 101 insertions(+), 119 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/36381/1
diff --git a/src/mainboard/asrock/h110m/acpi/superio.asl b/src/mainboard/asrock/h110m/acpi/superio.asl index b671e3c..8b13789 100644 --- a/src/mainboard/asrock/h110m/acpi/superio.asl +++ b/src/mainboard/asrock/h110m/acpi/superio.asl @@ -1,26 +1 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Tristan Corrick tristan@corrick.kiwi - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */
-#define SUPERIO_DEV SIO0 -#define SUPERIO_PNP_BASE 0x2e -#define NCT6776_SHOW_PP -#define NCT6776_SHOW_SP1 -#define NCT6776_SHOW_KBC -#define NCT6776_SHOW_HWM - -#undef NCT6776_SHOW_GPIO - -#include <superio/nuvoton/nct6776/acpi/superio.asl> diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 425bc63..8854e76 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -322,101 +322,108 @@ device pci 1e.6 off end # SDCard device pci 1f.0 on # LPC bridge subsystemid 0x1849 0x1a43 - chip superio/nuvoton/nct6791d - device pnp 2e.0 off end # Floppy - device pnp 2e.1 on - # Global Control Registers - # Device IRQ Polarity - irq 0x13 = 0x00 - irq 0x14 = 0x00 - # Global Option - irq 0x24 = 0xfb - irq 0x27 = 0x10 - # Multi Function - irq 0x1a = 0xb0 - irq 0x1b = 0xe6 - irq 0x2a = 0x04 - irq 0x2c = 0x40 - irq 0x2d = 0x03
- # Parallel Port - io 0x60 = 0x0378 - irq 0x70 = 7 - drq 0x74 = 4 # No DMA - irq 0xf0 = 0x3c # Printer mode - end - device pnp 2e.2 on # UART A - io 0x60 = 0x03f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # IR - io 0x60 = 0x02f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 KBC - io 0x60 = 0x0060 - io 0x62 = 0x0064 - irq 0x70 = 1 # Keyboard - irq 0x72 = 12 # Mouse - end - device pnp 2e.6 off end # CIR - device pnp 2e.7 on # GPIO6 - irq 0xf6 = 0xff - irq 0xf7 = 0xff - irq 0xf8 = 0xff - end - device pnp 2e.107 on # GPIO7 - irq 0xe0 = 0x7f - irq 0xe1 = 0x0d - end - device pnp 2e.207 on # GPIO8 - irq 0xe6 = 0xff - irq 0xe7 = 0xff - irq 0xed = 0xff - end - device pnp 2e.8 off end # WDT - device pnp 2e.108 on end # GPIO0 - device pnp 2e.308 off end # GPIO base - device pnp 2e.408 off end # WDTMEM - device pnp 2e.708 on end # GPIO1 - device pnp 2e.9 on end # GPIO2 - device pnp 2e.109 on # GPIO3 - irq 0xe4 = 0x7b - irq 0xe5 = 0x02 - irq 0xea = 0x04 - end - device pnp 2e.209 on # GPIO4 - irq 0xf0 = 0x7f - irq 0xf1 = 0x80 - end - device pnp 2e.309 on # GPIO5 - irq 0xf4 = 0xdf - irq 0xf5 = 0xd5 - end - device pnp 2e.a on - # Power RAM in S3 and let the PCH - # handle power failure actions - irq 0xe4 = 0x70 - # Set HWM reset source to LRESET# - irq 0xe7 = 0x01 - end # ACPI - device pnp 2e.b on # HWM, LED - io 0x60 = 0x0290 - io 0x62 = 0 - irq 0x70 = 0 - end - device pnp 2e.d off end # BCLK, WDT2, WDT_MEM - device pnp 2e.e off end # CIR wake-up - device pnp 2e.f off end # GPIO PP/OD - device pnp 2e.14 off end # SVID, Port 80 UART - device pnp 2e.16 off end # DS5 - device pnp 2e.116 off end # DS3 - device pnp 2e.316 on end # PCHDSW - device pnp 2e.416 off end # DSWWOPT - device pnp 2e.516 on end # DS3OPT - device pnp 2e.616 on end # DSDSS - device pnp 2e.716 off end # DSPU - end # superio/nuvoton/nct6791d + chip superio/common + device pnp 2e.0 on # passes SIO base addr to SSDT gen + + chip superio/nuvoton/nct6791d + device pnp 2e.1 on + # Global Control Registers + # Device IRQ Polarity + irq 0x13 = 0x00 + irq 0x14 = 0x00 + # Global Option + irq 0x24 = 0xfb + irq 0x27 = 0x10 + # Multi Function + irq 0x1a = 0xb0 + irq 0x1b = 0xe6 + irq 0x2a = 0x04 + irq 0x2c = 0x40 + irq 0x2d = 0x03 + + # Parallel Port + io 0x60 = 0x0378 + irq 0x70 = 7 + drq 0x74 = 4 # No DMA + irq 0xf0 = 0x3c # Printer mode + end + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # IR + io 0x60 = 0x02f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 KBC + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # Keyboard + irq 0x72 = 12 # Mouse + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 on # GPIO6 + irq 0xf6 = 0xff + irq 0xf7 = 0xff + irq 0xf8 = 0xff + end + device pnp 2e.107 on # GPIO7 + irq 0xe0 = 0x7f + irq 0xe1 = 0x0d + end + device pnp 2e.207 on # GPIO8 + irq 0xe6 = 0xff + irq 0xe7 = 0xff + irq 0xed = 0xff + end + device pnp 2e.8 off end # WDT + device pnp 2e.108 on end # GPIO0 + device pnp 2e.308 off end # GPIO base + device pnp 2e.408 off end # WDTMEM + device pnp 2e.708 on end # GPIO1 + device pnp 2e.9 on end # GPIO2 + device pnp 2e.109 on # GPIO3 + irq 0xe4 = 0x7b + irq 0xe5 = 0x02 + irq 0xea = 0x04 + end + device pnp 2e.209 on # GPIO4 + irq 0xf0 = 0x7f + irq 0xf1 = 0x80 + end + device pnp 2e.309 on # GPIO5 + irq 0xf4 = 0xdf + irq 0xf5 = 0xd5 + end + device pnp 2e.a on + # Power RAM in S3 and let the PCH + # handle power failure actions + irq 0xe4 = 0x70 + # Set HWM reset source to LRESET# + irq 0xe7 = 0x01 + end # ACPI + device pnp 2e.b on # HWM, LED + io 0x60 = 0x0290 + io 0x62 = 0 + irq 0x70 = 0 + end + device pnp 2e.d off end # BCLK, WDT2, WDT_MEM + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID, Port 80 UART + device pnp 2e.16 off end # DS5 + device pnp 2e.116 off end # DS3 + device pnp 2e.316 on end # PCHDSW + device pnp 2e.416 off end # DSWWOPT + device pnp 2e.516 on end # DS3OPT + device pnp 2e.616 on end # DSDSS + device pnp 2e.716 off end # DSPU + end # chip superio/nuvoton/nct6791d + + end # device pnp 2e.0 + end # chip superio/common + chip drivers/pc80/tpm device pnp 4e.0 on end # TPM module end
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36381 )
Change subject: mb/asrock/h110m: use SuperIO acpigen ......................................................................
Patch Set 1:
This change is ready for review.
Hello Patrick Rudolph, Felix Held, Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36381
to look at the new patch set (#2).
Change subject: [WIP] mb/asrock/h110m: use SuperIO acpigen ......................................................................
[WIP] mb/asrock/h110m: use SuperIO acpigen
Change-Id: I57b67d10968e5e035536bcb0d8329ce09d50194b Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/asrock/h110m/acpi/superio.asl M src/mainboard/asrock/h110m/devicetree.cb 2 files changed, 101 insertions(+), 119 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/36381/2
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36381 )
Change subject: [WIP] mb/asrock/h110m: use SuperIO acpigen ......................................................................
Patch Set 2:
After applying the patch, the following messages appeared in the coreboot console:
LPC: Opened IO window LGIR2: base 2e size 2 LPC: Opened IO window LGIR3: base 378 size 8 LPC: Cannot open IO window: 3f8 size 8 No more IO windows LPC: Cannot open IO window: 2f8 size 8 No more IO windows LPC: Cannot open IO window: 60 size 1 No more IO windows LPC: Cannot open IO window: 64 size 1 No more IO windows LPC: Cannot open IO window: 0 size 8 No more IO windows LPC: Cannot open IO window: 0 size 8 No more IO windows LPC: Cannot open IO window: 290 size 2 No more IO windows LPC: Cannot open IO window: 0 size 2 No more IO windows LPC: Cannot open IO window: 0 size 8 No more IO windows
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36381 )
Change subject: [WIP] mb/asrock/h110m: use SuperIO acpigen ......................................................................
Patch Set 2:
Patch Set 2:
After applying the patch, the following messages appeared in the coreboot console:
LPC: Opened IO window LGIR2: base 2e size 2 LPC: Opened IO window LGIR3: base 378 size 8 LPC: Cannot open IO window: 3f8 size 8 No more IO windows LPC: Cannot open IO window: 2f8 size 8 No more IO windows LPC: Cannot open IO window: 60 size 1 No more IO windows LPC: Cannot open IO window: 64 size 1 No more IO windows LPC: Cannot open IO window: 0 size 8 No more IO windows LPC: Cannot open IO window: 0 size 8 No more IO windows LPC: Cannot open IO window: 290 size 2 No more IO windows LPC: Cannot open IO window: 0 size 2 No more IO windows LPC: Cannot open IO window: 0 size 8 No more IO windows
The code generating the errors was written by Intel TM without knownledge how hardware works. If the LPC decode ranges were correct before using the superio ssdtgen you can ignore the warnings.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36381 )
Change subject: [WIP] mb/asrock/h110m: use SuperIO acpigen ......................................................................
Patch Set 2: Code-Review+1
The code generating the errors was written by Intel TM without knownledge how hardware works. If the LPC decode ranges were correct before using the superio ssdtgen you can ignore the warnings.
ouch, do they try to use programmable lpc io decode ranges for components using the fixed function lpd io range decodes?! if so, this should be fixed...
the patch itself looks good to me
Hello Patrick Rudolph, Felix Held, Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36381
to look at the new patch set (#3).
Change subject: mb/asrock/h110m: use SSDT generator for SuperIO ......................................................................
mb/asrock/h110m: use SSDT generator for SuperIO
Modifies the device tree to use the ACPI SSDT generator[1] for NCT6791D SuperIO, dropping the need to include code from the superio.asl, which was inherited from another chip (NCT6776) and required fixes. SSDT gen support for Nuvoton NCT6791D chip was added in the previous patch [2].
[1] https://review.coreboot.org/c/coreboot/+/33033 [2] https://review.coreboot.org/c/coreboot/+/36379
Change-Id: I57b67d10968e5e035536bcb0d8329ce09d50194b Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/asrock/h110m/acpi/superio.asl M src/mainboard/asrock/h110m/devicetree.cb 2 files changed, 101 insertions(+), 119 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/36381/3
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36381 )
Change subject: mb/asrock/h110m: use SSDT generator for SuperIO ......................................................................
Patch Set 3:
Thanks for the review
Patch Set 2: Code-Review+1
The code generating the errors was written by Intel TM without knownledge how hardware works. If the LPC decode ranges were correct before using the superio ssdtgen you can ignore the warnings.
Do you mean LPC IO ranges that are set using genX_dec in https://github.com/coreboot/coreboot/blob/master/src/soc/intel/skylake/lpc.c... ?
ouch, do they try to use programmable lpc io decode ranges for components using the fixed function lpd io range decodes?! if so, this should be fixed...
the patch itself looks good to me
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36381 )
Change subject: mb/asrock/h110m: use SSDT generator for SuperIO ......................................................................
Patch Set 3: Code-Review+2
Do you mean LPC IO ranges that are set using genX_dec in https://github.com/coreboot/coreboot/blob/master/src/soc/intel/skylake/lpc.c... ?
Those are the generic ones. For peripherals like the SIO or EC configuration access, IO-mapped serial, parallel and floppy disk controller ports the decodes can just be enabled by flipping the corresponding bits in the IO enable register in the LPC PCI device. If something can be covered by the specific ones, there's no need to use and basically waste a generic one for that
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36381 )
Change subject: mb/asrock/h110m: use SSDT generator for SuperIO ......................................................................
mb/asrock/h110m: use SSDT generator for SuperIO
Modifies the device tree to use the ACPI SSDT generator[1] for NCT6791D SuperIO, dropping the need to include code from the superio.asl, which was inherited from another chip (NCT6776) and required fixes. SSDT gen support for Nuvoton NCT6791D chip was added in the previous patch [2].
[1] https://review.coreboot.org/c/coreboot/+/33033 [2] https://review.coreboot.org/c/coreboot/+/36379
Change-Id: I57b67d10968e5e035536bcb0d8329ce09d50194b Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/36381 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Felix Held felix-coreboot@felixheld.de --- M src/mainboard/asrock/h110m/acpi/superio.asl M src/mainboard/asrock/h110m/devicetree.cb 2 files changed, 101 insertions(+), 119 deletions(-)
Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved
diff --git a/src/mainboard/asrock/h110m/acpi/superio.asl b/src/mainboard/asrock/h110m/acpi/superio.asl index b671e3c..8b13789 100644 --- a/src/mainboard/asrock/h110m/acpi/superio.asl +++ b/src/mainboard/asrock/h110m/acpi/superio.asl @@ -1,26 +1 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Tristan Corrick tristan@corrick.kiwi - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */
-#define SUPERIO_DEV SIO0 -#define SUPERIO_PNP_BASE 0x2e -#define NCT6776_SHOW_PP -#define NCT6776_SHOW_SP1 -#define NCT6776_SHOW_KBC -#define NCT6776_SHOW_HWM - -#undef NCT6776_SHOW_GPIO - -#include <superio/nuvoton/nct6776/acpi/superio.asl> diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index b2a2d72..2d6b951 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -326,101 +326,108 @@ device pci 1e.6 off end # SDCard device pci 1f.0 on # LPC bridge subsystemid 0x1849 0x1a43 - chip superio/nuvoton/nct6791d - device pnp 2e.0 off end # Floppy - device pnp 2e.1 on - # Global Control Registers - # Device IRQ Polarity - irq 0x13 = 0x00 - irq 0x14 = 0x00 - # Global Option - irq 0x24 = 0xfb - irq 0x27 = 0x10 - # Multi Function - irq 0x1a = 0xb0 - irq 0x1b = 0xe6 - irq 0x2a = 0x04 - irq 0x2c = 0x40 - irq 0x2d = 0x03
- # Parallel Port - io 0x60 = 0x0378 - irq 0x70 = 7 - drq 0x74 = 4 # No DMA - irq 0xf0 = 0x3c # Printer mode - end - device pnp 2e.2 on # UART A - io 0x60 = 0x03f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # IR - io 0x60 = 0x02f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 KBC - io 0x60 = 0x0060 - io 0x62 = 0x0064 - irq 0x70 = 1 # Keyboard - irq 0x72 = 12 # Mouse - end - device pnp 2e.6 off end # CIR - device pnp 2e.7 on # GPIO6 - irq 0xf6 = 0xff - irq 0xf7 = 0xff - irq 0xf8 = 0xff - end - device pnp 2e.107 on # GPIO7 - irq 0xe0 = 0x7f - irq 0xe1 = 0x0d - end - device pnp 2e.207 on # GPIO8 - irq 0xe6 = 0xff - irq 0xe7 = 0xff - irq 0xed = 0xff - end - device pnp 2e.8 off end # WDT - device pnp 2e.108 on end # GPIO0 - device pnp 2e.308 off end # GPIO base - device pnp 2e.408 off end # WDTMEM - device pnp 2e.708 on end # GPIO1 - device pnp 2e.9 on end # GPIO2 - device pnp 2e.109 on # GPIO3 - irq 0xe4 = 0x7b - irq 0xe5 = 0x02 - irq 0xea = 0x04 - end - device pnp 2e.209 on # GPIO4 - irq 0xf0 = 0x7f - irq 0xf1 = 0x80 - end - device pnp 2e.309 on # GPIO5 - irq 0xf4 = 0xdf - irq 0xf5 = 0xd5 - end - device pnp 2e.a on - # Power RAM in S3 and let the PCH - # handle power failure actions - irq 0xe4 = 0x70 - # Set HWM reset source to LRESET# - irq 0xe7 = 0x01 - end # ACPI - device pnp 2e.b on # HWM, LED - io 0x60 = 0x0290 - io 0x62 = 0 - irq 0x70 = 0 - end - device pnp 2e.d off end # BCLK, WDT2, WDT_MEM - device pnp 2e.e off end # CIR wake-up - device pnp 2e.f off end # GPIO PP/OD - device pnp 2e.14 off end # SVID, Port 80 UART - device pnp 2e.16 off end # DS5 - device pnp 2e.116 off end # DS3 - device pnp 2e.316 on end # PCHDSW - device pnp 2e.416 off end # DSWWOPT - device pnp 2e.516 on end # DS3OPT - device pnp 2e.616 on end # DSDSS - device pnp 2e.716 off end # DSPU - end # superio/nuvoton/nct6791d + chip superio/common + device pnp 2e.0 on # passes SIO base addr to SSDT gen + + chip superio/nuvoton/nct6791d + device pnp 2e.1 on + # Global Control Registers + # Device IRQ Polarity + irq 0x13 = 0x00 + irq 0x14 = 0x00 + # Global Option + irq 0x24 = 0xfb + irq 0x27 = 0x10 + # Multi Function + irq 0x1a = 0xb0 + irq 0x1b = 0xe6 + irq 0x2a = 0x04 + irq 0x2c = 0x40 + irq 0x2d = 0x03 + + # Parallel Port + io 0x60 = 0x0378 + irq 0x70 = 7 + drq 0x74 = 4 # No DMA + irq 0xf0 = 0x3c # Printer mode + end + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # IR + io 0x60 = 0x02f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 KBC + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # Keyboard + irq 0x72 = 12 # Mouse + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 on # GPIO6 + irq 0xf6 = 0xff + irq 0xf7 = 0xff + irq 0xf8 = 0xff + end + device pnp 2e.107 on # GPIO7 + irq 0xe0 = 0x7f + irq 0xe1 = 0x0d + end + device pnp 2e.207 on # GPIO8 + irq 0xe6 = 0xff + irq 0xe7 = 0xff + irq 0xed = 0xff + end + device pnp 2e.8 off end # WDT + device pnp 2e.108 on end # GPIO0 + device pnp 2e.308 off end # GPIO base + device pnp 2e.408 off end # WDTMEM + device pnp 2e.708 on end # GPIO1 + device pnp 2e.9 on end # GPIO2 + device pnp 2e.109 on # GPIO3 + irq 0xe4 = 0x7b + irq 0xe5 = 0x02 + irq 0xea = 0x04 + end + device pnp 2e.209 on # GPIO4 + irq 0xf0 = 0x7f + irq 0xf1 = 0x80 + end + device pnp 2e.309 on # GPIO5 + irq 0xf4 = 0xdf + irq 0xf5 = 0xd5 + end + device pnp 2e.a on + # Power RAM in S3 and let the PCH + # handle power failure actions + irq 0xe4 = 0x70 + # Set HWM reset source to LRESET# + irq 0xe7 = 0x01 + end # ACPI + device pnp 2e.b on # HWM, LED + io 0x60 = 0x0290 + io 0x62 = 0 + irq 0x70 = 0 + end + device pnp 2e.d off end # BCLK, WDT2, WDT_MEM + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID, Port 80 UART + device pnp 2e.16 off end # DS5 + device pnp 2e.116 off end # DS3 + device pnp 2e.316 on end # PCHDSW + device pnp 2e.416 off end # DSWWOPT + device pnp 2e.516 on end # DS3OPT + device pnp 2e.616 on end # DSDSS + device pnp 2e.716 off end # DSPU + end # chip superio/nuvoton/nct6791d + + end # device pnp 2e.0 + end # chip superio/common + chip drivers/pc80/tpm device pnp 4e.0 on end # TPM module end
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Felix Held (Code Review) -
Maxim Polyakov (Code Review)
-
Patrick Rudolph (Code Review)