[S] Change in coreboot[main]: Kconfig: Place XIP components and FIT at high flash addresses

[Shuo Liu (Code Review)]

Attention is currently required from: Andrey Petrov, Angel Pons, Angel Pons, Arthur Heymans, Chen, Gang C, Christian Walter, Intel coreboot Reviewers, Johnny Lin, Jonathan Zhang, Julius Werner, Ronak Kanabar, Tim Chu, Yu-Ping Wu.

Shuo Liu has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/86570?usp=email )

Change subject: Kconfig: Place XIP components and FIT at high flash addresses
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Patch Set 10:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/86570/comment/78c9bde8_52794f41?usp... :
PS8, Line 9: CACHE_ROM_SIZE
> This makes no sense. […]

Sorry, I need to further clarify. Cache as RAM is composed of 2 parts, code and data, which share the total amount of footprint budget.

Code part - CodeRegionBase/Length - 16MiB here (UEFI uses 5MiB).
Data part - CONFIG_DCACHE_RAM_BASE/CONFIG_DCACHE_RAM_SIZE - ~2MiB.