Change in coreboot[master]: mb/sapphire/pureplatinumh61: Make devicetree prettier

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38062 )

Change subject: mb/sapphire/pureplatinumh61: Make devicetree prettier
......................................................................

mb/sapphire/pureplatinumh61: Make devicetree prettier

Align contents, and fix some redundant comments.

Change-Id: I0c9e98281aeb887308c3cbb421105b1faf922063
Signed-off-by: Angel Pons 
---
M src/mainboard/sapphire/pureplatinumh61/devicetree.cb
1 file changed, 26 insertions(+), 38 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/38062/1

diff --git a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb
index cb7ef9a..468c35a 100644
--- a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb
+++ b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb
@@ -30,7 +30,7 @@
    	end
    end
    device domain 0x0 on
-		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+		chip southbridge/intel/bd82x6x	# Intel Series 6 Cougar Point PCH
    		register "c2_latency" = "0x0065"
    		register "gen1_dec" = "0x000c0291"
    		register "gen2_dec" = "0x000c0a01"
@@ -46,48 +46,38 @@
    					{0x9f, READ_NO_ADDR},
    					{0xad, WRITE_NO_ADDR},
    					{0x04, WRITE_NO_ADDR}}"
-			device pci 16.0 on # Management Engine Interface 1
+			device pci 16.0 on	# Management Engine Interface 1
    			subsystemid 0x174b 0x1007
    		end
-			device pci 16.1 off # Management Engine Interface 2
-			end
-			device pci 16.2 off # Management Engine IDE-R
-			end
-			device pci 16.3 off # Management Engine KT
-			end
-			device pci 19.0 off # Intel Gigabit Ethernet
-			end
-			device pci 1a.0 on # USB2 EHCI #2
+			device pci 16.1 off end	# Management Engine Interface 2
+			device pci 16.2 off end	# Management Engine IDE-R
+			device pci 16.3 off end	# Management Engine KT
+			device pci 19.0 off end	# Intel Gigabit Ethernet
+			device pci 1a.0 on	# USB2 EHCI #2
    			subsystemid 0x174b 0x1007
    		end
-			device pci 1b.0 on # High Definition Audio Audio controller
+			device pci 1b.0 on	# HD Audio Controller
    			subsystemid 0x8086 0x1c20
    		end
-			device pci 1c.0 on # PCIe Port #1
+			device pci 1c.0 on	# PCIe Port #1
    			subsystemid 0x174b 0x1007
    		end
-			device pci 1c.1 off # PCIe Port #2
-			end
-			device pci 1c.2 off # PCIe Port #3
-			end
-			device pci 1c.3 off # PCIe Port #4
-			end
-			device pci 1c.4 on # PCIe Port #5
+			device pci 1c.1 off end	# PCIe Port #2
+			device pci 1c.2 off end	# PCIe Port #3
+			device pci 1c.3 off end	# PCIe Port #4
+			device pci 1c.4 on	# PCIe Port #5
    			subsystemid 0x174b 0x1007
    		end
-			device pci 1c.5 on # PCIe Port #6
+			device pci 1c.5 on	# PCIe Port #6
    			subsystemid 0x174b 0x1007
    		end
-			device pci 1c.6 off # PCIe Port #7
-			end
-			device pci 1c.7 off # PCIe Port #8
-			end
-			device pci 1d.0 on # USB2 EHCI #1
+			device pci 1c.6 off end	# PCIe Port #7
+			device pci 1c.7 off end	# PCIe Port #8
+			device pci 1d.0 on	# USB2 EHCI #1
    			subsystemid 0x174b 0x1007
    		end
-			device pci 1e.0 off # PCI bridge
-			end
-			device pci 1f.0 on # LPC bridge PCI-LPC bridge
+			device pci 1e.0 off end	# PCI bridge
+			device pci 1f.0 on	# LPC bridge
    			subsystemid 0x174b 0x1007
    			chip superio/fintek/f71808a
    				register "multi_function_register_0" = "0x00"
@@ -130,24 +120,22 @@
    				end
    			end
    		end
-			device pci 1f.2 on # SATA Controller 1
+			device pci 1f.2 on	# SATA Controller 1
    			subsystemid 0x174b 0x1007
    		end
-			device pci 1f.3 on # SMBus
+			device pci 1f.3 on	# SMBus
    			subsystemid 0x174b 0x1007
    		end
-			device pci 1f.5 off # SATA Controller 2
-			end
-			device pci 1f.6 off # Thermal
-			end
+			device pci 1f.5 off end	# SATA Controller 2
+			device pci 1f.6 off end	# Thermal
    	end
-		device pci 00.0 on # Host bridge Host bridge
+		device pci 00.0 on	# Host bridge
    		subsystemid 0x174b 0x1007
    	end
-		device pci 01.0 on # PCIe Bridge for discrete graphics
+		device pci 01.0 on	# PCIe Bridge for discrete graphics
    		subsystemid 0x174b 0x1007
    	end
-		device pci 02.0 on # Internal graphics VGA controller
+		device pci 02.0 on	# Internal graphics VGA controller
    		subsystemid 0x8086 0x2010
    	end
    end

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38062 )

Change subject: mb/sapphire/pureplatinumh61: Make devicetree prettier
......................................................................

Patch Set 1: Code-Review+2

[Nico Huber (Code Review)]

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38062 )

Change subject: mb/sapphire/pureplatinumh61: Make devicetree prettier
......................................................................

mb/sapphire/pureplatinumh61: Make devicetree prettier

Align contents, and fix some redundant comments.

Change-Id: I0c9e98281aeb887308c3cbb421105b1faf922063
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38062
Tested-by: build bot (Jenkins) 
Reviewed-by: Nico Huber 
---
M src/mainboard/sapphire/pureplatinumh61/devicetree.cb
1 file changed, 26 insertions(+), 38 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved

diff --git a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb
index cb7ef9a..468c35a 100644
--- a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb
+++ b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb
@@ -30,7 +30,7 @@
    	end
    end
    device domain 0x0 on
-		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+		chip southbridge/intel/bd82x6x	# Intel Series 6 Cougar Point PCH
    		register "c2_latency" = "0x0065"
    		register "gen1_dec" = "0x000c0291"
    		register "gen2_dec" = "0x000c0a01"
@@ -46,48 +46,38 @@
    					{0x9f, READ_NO_ADDR},
    					{0xad, WRITE_NO_ADDR},
    					{0x04, WRITE_NO_ADDR}}"
-			device pci 16.0 on # Management Engine Interface 1
+			device pci 16.0 on	# Management Engine Interface 1
    			subsystemid 0x174b 0x1007
    		end
-			device pci 16.1 off # Management Engine Interface 2
-			end
-			device pci 16.2 off # Management Engine IDE-R
-			end
-			device pci 16.3 off # Management Engine KT
-			end
-			device pci 19.0 off # Intel Gigabit Ethernet
-			end
-			device pci 1a.0 on # USB2 EHCI #2
+			device pci 16.1 off end	# Management Engine Interface 2
+			device pci 16.2 off end	# Management Engine IDE-R
+			device pci 16.3 off end	# Management Engine KT
+			device pci 19.0 off end	# Intel Gigabit Ethernet
+			device pci 1a.0 on	# USB2 EHCI #2
    			subsystemid 0x174b 0x1007
    		end
-			device pci 1b.0 on # High Definition Audio Audio controller
+			device pci 1b.0 on	# HD Audio Controller
    			subsystemid 0x8086 0x1c20
    		end
-			device pci 1c.0 on # PCIe Port #1
+			device pci 1c.0 on	# PCIe Port #1
    			subsystemid 0x174b 0x1007
    		end
-			device pci 1c.1 off # PCIe Port #2
-			end
-			device pci 1c.2 off # PCIe Port #3
-			end
-			device pci 1c.3 off # PCIe Port #4
-			end
-			device pci 1c.4 on # PCIe Port #5
+			device pci 1c.1 off end	# PCIe Port #2
+			device pci 1c.2 off end	# PCIe Port #3
+			device pci 1c.3 off end	# PCIe Port #4
+			device pci 1c.4 on	# PCIe Port #5
    			subsystemid 0x174b 0x1007
    		end
-			device pci 1c.5 on # PCIe Port #6
+			device pci 1c.5 on	# PCIe Port #6
    			subsystemid 0x174b 0x1007
    		end
-			device pci 1c.6 off # PCIe Port #7
-			end
-			device pci 1c.7 off # PCIe Port #8
-			end
-			device pci 1d.0 on # USB2 EHCI #1
+			device pci 1c.6 off end	# PCIe Port #7
+			device pci 1c.7 off end	# PCIe Port #8
+			device pci 1d.0 on	# USB2 EHCI #1
    			subsystemid 0x174b 0x1007
    		end
-			device pci 1e.0 off # PCI bridge
-			end
-			device pci 1f.0 on # LPC bridge PCI-LPC bridge
+			device pci 1e.0 off end	# PCI bridge
+			device pci 1f.0 on	# LPC bridge
    			subsystemid 0x174b 0x1007
    			chip superio/fintek/f71808a
    				register "multi_function_register_0" = "0x00"
@@ -130,24 +120,22 @@
    				end
    			end
    		end
-			device pci 1f.2 on # SATA Controller 1
+			device pci 1f.2 on	# SATA Controller 1
    			subsystemid 0x174b 0x1007
    		end
-			device pci 1f.3 on # SMBus
+			device pci 1f.3 on	# SMBus
    			subsystemid 0x174b 0x1007
    		end
-			device pci 1f.5 off # SATA Controller 2
-			end
-			device pci 1f.6 off # Thermal
-			end
+			device pci 1f.5 off end	# SATA Controller 2
+			device pci 1f.6 off end	# Thermal
    	end
-		device pci 00.0 on # Host bridge Host bridge
+		device pci 00.0 on	# Host bridge
    		subsystemid 0x174b 0x1007
    	end
-		device pci 01.0 on # PCIe Bridge for discrete graphics
+		device pci 01.0 on	# PCIe Bridge for discrete graphics
    		subsystemid 0x174b 0x1007
    	end
-		device pci 02.0 on # Internal graphics VGA controller
+		device pci 02.0 on	# Internal graphics VGA controller
    		subsystemid 0x8086 0x2010
    	end
    end