[M] Change in coreboot[main]: soc/intel: Allow zero values for PMC GPE0 DW registers

[Matt DeVillier (Code Review)]

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Eric Lai, Intel coreboot Reviewers, Jakub Czapiga, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Nick Vaccaro, Pranava Y N, Sean Rhodes, Tarun, Werner Zeh.

Matt DeVillier has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86164?usp=email )

Change subject: soc/intel: Allow zero values for PMC GPE0 DW registers
......................................................................

Patch Set 5:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/86164/comment/a08e6039_fd2e7cd0?usp... :
PS5, Line 11: This prevented platforms from
            : disabling GPE routing via PMC by setting all DW values to zero.
no, it prevented platforms from using the default GPE routing by not programming the routes in devicetree

File src/soc/intel/alderlake/pmutil.c:

https://review.coreboot.org/c/coreboot/+/86164/comment/8f0615de_04c1b85e?usp... :
PS3, Line 164: override
> > do we really need this here? there's already another printk in this case (PMC: Using default GPE route.)
>
> `PMC: Using default GPE route` this often mislead as default value from baseboard but doesn't convey if we are using all zero value which is ideally what you wish to avoid here. All zero values for all dwords is not valid.

right, but the zeros are not being programmed - see `pmc_gpe_init` in `src/soc/intel/common/block/pmc/pmclib.c`. If all zeros are passed in, then dw0 == dw1 == dw2, and the POR values are read from `GPIO_GPE_CFG` and programmed into `MISCCFG`.