Change in coreboot[master]: [RFC] soc/intel/{adl,ehl,icl,jsl,tgl}: Invert `eist_enabled`
Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50426 )
Change subject: [RFC] soc/intel/{adl,ehl,icl,jsl,tgl}: Invert `eist_enabled` ......................................................................
[RFC] soc/intel/{adl,ehl,icl,jsl,tgl}: Invert `eist_enabled`
This enables EIST and P states by default for all boards using these platforms.
Change-Id: I313194edb3795962a42eebde9683579abc078851 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/alderlake/acpi.c M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/cpu.c M src/soc/intel/elkhartlake/acpi.c M src/soc/intel/elkhartlake/chip.h M src/soc/intel/elkhartlake/cpu.c M src/soc/intel/icelake/acpi.c M src/soc/intel/icelake/chip.h M src/soc/intel/icelake/cpu.c M src/soc/intel/jasperlake/acpi.c M src/soc/intel/jasperlake/chip.h M src/soc/intel/jasperlake/cpu.c M src/soc/intel/tigerlake/acpi.c M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/cpu.c 15 files changed, 15 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/50426/1
diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c index 1536de1..fc16e90 100644 --- a/src/soc/intel/alderlake/acpi.c +++ b/src/soc/intel/alderlake/acpi.c @@ -141,7 +141,7 @@ { config_t *config = config_of_soc();
- if (config->eist_enable) + if (!config->eist_disable) /* Generate P-state tables */ generate_p_state_entries(core_id, cores_per_package); } diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 13e77cf..f049c0c 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -154,8 +154,7 @@ /* PL2 Override value in Watts */ uint32_t tdp_pl2_override;
- /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ - uint8_t eist_enable; + uint8_t eist_disable;
/* Enable C6 DRAM */ uint8_t enable_c6dram; diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index 32f5ea2..4e8255f 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -41,7 +41,7 @@ wrmsr(IA32_MISC_ENABLE, msr);
/* Set EIST status */ - cpu_set_eist(conf->eist_enable); + cpu_set_eist(!conf->eist_disable);
/* Disable Thermal interrupts */ msr.lo = 0; diff --git a/src/soc/intel/elkhartlake/acpi.c b/src/soc/intel/elkhartlake/acpi.c index 0c87cfd..2850944 100644 --- a/src/soc/intel/elkhartlake/acpi.c +++ b/src/soc/intel/elkhartlake/acpi.c @@ -140,7 +140,7 @@ { config_t *config = config_of_soc();
- if (config->eist_enable) + if (!config->eist_disable) /* Generate P-state tables */ generate_p_state_entries(core_id, cores_per_package); } diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index 1d97b36..5be010d 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -137,8 +137,7 @@ * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled;
- /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ - uint8_t eist_enable; + uint8_t eist_disable;
/* Enable C6 DRAM */ uint8_t enable_c6dram; diff --git a/src/soc/intel/elkhartlake/cpu.c b/src/soc/intel/elkhartlake/cpu.c index 984f7f2..fd6273c 100644 --- a/src/soc/intel/elkhartlake/cpu.c +++ b/src/soc/intel/elkhartlake/cpu.c @@ -35,7 +35,7 @@ wrmsr(IA32_MISC_ENABLE, msr);
/* Set EIST status */ - cpu_set_eist(conf->eist_enable); + cpu_set_eist(!conf->eist_disable);
/* Disable Thermal interrupts */ msr.lo = 0; diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index 6240f68..cd62cc1 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -137,7 +137,7 @@ { config_t *config = config_of_soc();
- if (config->eist_enable) + if (!config->eist_disable) /* Generate P-state tables */ generate_p_state_entries(core_id, cores_per_package); } diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index 64bc70b..634c73c 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -145,8 +145,7 @@ * 11b - Reserved */ uint8_t SendVrMbxCmd;
- /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ - uint8_t eist_enable; + uint8_t eist_disable;
/* Enable C6 DRAM */ uint8_t enable_c6dram; diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index dd70c85..6e74574 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -35,7 +35,7 @@ wrmsr(IA32_MISC_ENABLE, msr);
/* Set EIST status */ - cpu_set_eist(conf->eist_enable); + cpu_set_eist(!conf->eist_disable);
/* Disable Thermal interrupts */ msr.lo = 0; diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c index 1a9286a..84a6ac1 100644 --- a/src/soc/intel/jasperlake/acpi.c +++ b/src/soc/intel/jasperlake/acpi.c @@ -140,7 +140,7 @@ { config_t *config = config_of_soc();
- if (config->eist_enable) + if (!config->eist_disable) /* Generate P-state tables */ generate_p_state_entries(core_id, cores_per_package); } diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 6e52efd..0a10e6f 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -137,8 +137,7 @@ * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled;
- /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ - uint8_t eist_enable; + uint8_t eist_disable;
/* Enable C6 DRAM */ uint8_t enable_c6dram; diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c index a3790e1..52fe072 100644 --- a/src/soc/intel/jasperlake/cpu.c +++ b/src/soc/intel/jasperlake/cpu.c @@ -35,7 +35,7 @@ wrmsr(IA32_MISC_ENABLE, msr);
/* Set EIST status */ - cpu_set_eist(conf->eist_enable); + cpu_set_eist(!conf->eist_disable);
/* Disable Thermal interrupts */ msr.lo = 0; diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index d81efb9..814a78e 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -140,7 +140,7 @@ { config_t *config = config_of_soc();
- if (config->eist_enable) + if (!config->eist_disable) /* Generate P-state tables */ generate_p_state_entries(core_id, cores_per_package); } diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index edc7160..7eb34f1 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -271,8 +271,7 @@ * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled;
- /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ - uint8_t eist_enable; + uint8_t eist_disable;
/* Enable C6 DRAM */ uint8_t enable_c6dram; diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c index 974401f..a38f3ce 100644 --- a/src/soc/intel/tigerlake/cpu.c +++ b/src/soc/intel/tigerlake/cpu.c @@ -41,7 +41,7 @@ wrmsr(IA32_MISC_ENABLE, msr);
/* Set EIST status */ - cpu_set_eist(conf->eist_enable); + cpu_set_eist(!conf->eist_disable);
/* Disable Thermal interrupts */ msr.lo = 0;
-
Angel Pons (Code Review)