[S] Change in coreboot[master]: mb/google/nissa/var/pujjo: Disable PCH USB2 phy power gating for pujjo

[Leo Chou (Code Review)]

Leo Chou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/67531 )

Change subject: mb/google/nissa/var/pujjo: Disable PCH USB2 phy power gating for pujjo
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mb/google/nissa/var/pujjo: Disable PCH USB2 phy power gating for pujjo

The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for pujjo board. Please refer Intel doc#723158 for
more information.

BUG=b:245970842
TEST=Verify on pujjo boards.

Signed-off-by: Leo Chou 
Change-Id: Iec05c440410812fa7999d2314c8bf4a51b9f429a
---
M src/mainboard/google/brya/variants/pujjo/overridetree.cb
1 file changed, 21 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/67531/1

diff --git a/src/mainboard/google/brya/variants/pujjo/overridetree.cb b/src/mainboard/google/brya/variants/pujjo/overridetree.cb
index 14164bc..aa9e71d 100644
--- a/src/mainboard/google/brya/variants/pujjo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjo/overridetree.cb
@@ -33,6 +33,10 @@
 end

chip soc/intel/alderlake
+        # As per Intel Advisory doc#723158, the change is required to prevent possible
+        # display flickering issue.
+        register "usb2_phy_sus_pg_disable" = "1"
+
    # Acoustic settings
    register "acoustic_noise_mitigation" = "1"
    register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8"