Change in coreboot[master]: soc/intel/alderlake: Select number of I/O for ADL-N

[Usha P (Code Review)]

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph.
Usha P has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59752 )

Change subject: soc/intel/alderlake: Select number of I/O for ADL-N
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soc/intel/alderlake: Select number of I/O for ADL-N

Select number of I/O based on PCH for Alder Lake-N

Signed-off-by: Usha P 
Change-Id: I7ebbcdcdb1ccc34b80ec71ac3e591fe4ad6b1904
---
M src/soc/intel/alderlake/Kconfig
1 file changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/59752/1

diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index a6e2672..941a677 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -174,6 +174,7 @@
 config MAX_PCH_ROOT_PORTS
    int
    default 10 if SOC_INTEL_ALDERLAKE_PCH_M
+	default 9 if SOC_INTEL_ALDERLAKE_PCH_N
    default 12

config MAX_CPU_ROOT_PORTS
@@ -188,11 +189,13 @@
 config MAX_PCIE_CLOCK_SRC
    int
    default 6 if SOC_INTEL_ALDERLAKE_PCH_M
+	default 5 if SOC_INTEL_ALDERLAKE_PCH_N
    default 7

config MAX_PCIE_CLOCK_REQ
    int
    default 6 if SOC_INTEL_ALDERLAKE_PCH_M
+	default 5 if SOC_INTEL_ALDERLAKE_PCH_N
    default 10

config SMM_TSEG_SIZE