New patch to review for coreboot: 062b82c Rename SANDYBRIDGE_BCLK to NEHALEM_BCLK in 2065x.
Vladimir Serbinenko (phcoder@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4045
-gerrit
commit 062b82c0deba7c9633ca54aebefbf972d6b490d2 Author: Vladimir Serbinenko phcoder@gmail.com Date: Tue Nov 12 23:32:52 2013 +0100
Rename SANDYBRIDGE_BCLK to NEHALEM_BCLK in 2065x.
2065x is with nehalem and not sandybridge.
I don't care much eitherway but it clears some confusion.
Change-Id: I0ce8574db66990f529a123ae984a4ecda497f5a1 Signed-off-by: Vladimir Serbinenko phcoder@gmail.com --- src/cpu/intel/model_2065x/acpi.c | 4 ++-- src/cpu/intel/model_2065x/model_2065x.h | 2 +- src/cpu/intel/model_2065x/model_2065x_init.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/cpu/intel/model_2065x/acpi.c b/src/cpu/intel/model_2065x/acpi.c index 8483812..fa0dc95 100644 --- a/src/cpu/intel/model_2065x/acpi.c +++ b/src/cpu/intel/model_2065x/acpi.c @@ -237,7 +237,7 @@ static int generate_P_state_entries(int core, int cores_per_package) /* Max Non-Turbo Ratio */ ratio_max = (msr.lo >> 8) & 0xff; } - clock_max = ratio_max * SANDYBRIDGE_BCLK + ratio_max / 3; + clock_max = ratio_max * NEHALEM_BCLK + ratio_max / 3;
/* Calculate CPU TDP in mW */ power_max = 25000; @@ -298,7 +298,7 @@ static int generate_P_state_entries(int core, int cores_per_package)
/* Calculate power at this ratio */ power = calculate_power(power_max, ratio_max, ratio); - clock = ratio * SANDYBRIDGE_BCLK + ratio / 3; + clock = ratio * NEHALEM_BCLK + ratio / 3;
len_pss += acpigen_write_PSS_package( clock, /*MHz*/ diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index 18a45d8..813548e 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -23,7 +23,7 @@ #define _CPU_INTEL_MODEL_2065X_H
/* SandyBridge/IvyBridge bus clock is fixed at 100MHz */ -#define SANDYBRIDGE_BCLK 133 +#define NEHALEM_BCLK 133
#define IA32_FEATURE_CONTROL 0x3a #define CPUID_VMX (1 << 5) diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index 4c88e44..0fd1bf0 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -311,7 +311,7 @@ static void set_max_ratio(void) wrmsr(IA32_PERF_CTL, perf_ctl);
printk(BIOS_DEBUG, "model_x06ax: frequency set to %d\n", - ((perf_ctl.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK); + ((perf_ctl.lo >> 8) & 0xff) * NEHALEM_BCLK); }
static void set_energy_perf_bias(u8 policy)
-
Vladimir Serbinenko