Change in coreboot[master]: vc/amd/agesa/f16kb: raise the DDR3 UDIMM Freq limit 1333MHz values to...
Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44461 )
Change subject: vc/amd/agesa/f16kb: raise the DDR3 UDIMM Freq limit 1333MHz values to 1600MHz ......................................................................
vc/amd/agesa/f16kb: raise the DDR3 UDIMM Freq limit 1333MHz values to 1600MHz
AMD f16kb boards should be perfectly capable of working at 1600MHz RAM speeds even with two DDR3 UDIMM modules. These low 1333MHz limits aren't justified, should raise them to 1600MHz and let the memory training code to do the rest.
Successfully tested on ASUS AM1I-A and two Crucial BLT8G3D1869DT1TX0 UDIMMs, together with the other related AMD_XMP changes which help to enable 1600MHz.
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I2a9da4e594ab3dc38b5ba87520633cbd01c9ce01 --- M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpUkb3.c 1 file changed, 6 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/44461/1
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpUkb3.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpUkb3.c index 7e9b64e..3bc99bf 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpUkb3.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpUkb3.c @@ -92,8 +92,8 @@ {{_2DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, {{_2DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, {{_2DIMM, 2, 2, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, - {{_2DIMM, 2, 1, 1, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, - {{_2DIMM, 2, 0, 2, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, + {{_2DIMM, 2, 1, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, + {{_2DIMM, 2, 0, 2, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, }; CONST PSC_TBL_ENTRY KBMaxFreqTblEntU6L = { {PSCFG_MAXFREQ, UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY}, @@ -111,8 +111,8 @@ {{_2DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, {{_2DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, {{_2DIMM, 2, 2, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, - {{_2DIMM, 2, 1, 1, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, - {{_2DIMM, 2, 0, 2, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, + {{_2DIMM, 2, 1, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, + {{_2DIMM, 2, 0, 2, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, }; CONST PSC_TBL_ENTRY KBMaxFreqTblEntMicroSrvU6L = { {PSCFG_MAXFREQ, UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY}, @@ -130,8 +130,8 @@ {{_2DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, {{_2DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, {{_2DIMM, 2, 2, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, - {{_2DIMM, 2, 1, 1, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, - {{_2DIMM, 2, 0, 2, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, + {{_2DIMM, 2, 1, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, + {{_2DIMM, 2, 0, 2, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, }; CONST PSC_TBL_ENTRY KBMaxFreqTblEntU4L = { {PSCFG_MAXFREQ, UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY},
Mike Banon has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/44461 )
Change subject: vc/amd/agesa/f16kb: raise the UDIMM Freq limit 1333MHz values to 1600MHz ......................................................................
vc/amd/agesa/f16kb: raise the UDIMM Freq limit 1333MHz values to 1600MHz
AMD f16kb boards are perfectly capable of working at 1600MHz RAM speeds even with two DDR3 UDIMM modules. Low 1333MHz limits are not justified, raise them to 1600MHz and let the memory training code to do the rest.
Successfully tested on AM1I-A and two Crucial BLT8G3D1869DT1TX0 UDIMMs, together with related AMD_XMP changes (also required to get a 1600MHz).
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I2a9da4e594ab3dc38b5ba87520633cbd01c9ce01 --- M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpUkb3.c 1 file changed, 6 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/44461/2
Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44461 )
Change subject: vc/amd/agesa/f16kb: raise the UDIMM Freq limit 1333MHz values to 1600MHz ......................................................................
Patch Set 2:
Now AM1I-A can work on 1600MHz with two UDIMMs as well :)
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44461 )
Change subject: vc/amd/agesa/f16kb: raise the UDIMM Freq limit 1333MHz values to 1600MHz ......................................................................
Patch Set 2: Code-Review+1
(4 comments)
https://review.coreboot.org/c/coreboot/+/44461/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44461/2//COMMIT_MSG@7 PS2, Line 7: MHz MT/s (everywhere in the commit message)
https://review.coreboot.org/c/coreboot/+/44461/2//COMMIT_MSG@10 PS2, Line 10: two DDR3 UDIMM modules two DDR3 UDIMM modules *per channel*
https://review.coreboot.org/c/coreboot/+/44461/2/src/vendorcode/amd/agesa/f1... File src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpUkb3.c:
https://review.coreboot.org/c/coreboot/+/44461/2/src/vendorcode/amd/agesa/f1... PS2, Line 96: {{_2DIMM, 2, 0, 2, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, AFAIUI (and if the comments are true, this is the frequency limit for 2 DIMMs per channel when there's one single-rank and one dual-rank DIMM, or two dual-rank DIMMs. However, the AM1I-A does not support dual-channel operation, which is the reason why this change is necessary.
Please mention in the commit message that the AM1I-A only supports single-channel operation, with at most two DIMMs per channel.
https://www.asus.com/Motherboards/AM1IA/specifications/
https://review.coreboot.org/c/coreboot/+/44461/2/src/vendorcode/amd/agesa/f1... PS2, Line 108: STATIC CONST PSCFG_MAXFREQ_ENTRY ROMDATA MaxFreqKBMicroSrvUDIMM6L[] = { I'd recommend deduplicating the arrays. For another patch, though.
Hello build bot (Jenkins), Paul Menzel, Angel Pons, HAOUAS Elyes,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44461
to look at the new patch set (#3).
Change subject: vc/amd/agesa/f16kb: raise the UDIMM Freq limit 1333MT/s values to 1600MT/s ......................................................................
vc/amd/agesa/f16kb: raise the UDIMM Freq limit 1333MT/s values to 1600MT/s
AMD f16kb boards are perfectly capable of working at 1600MT/s RAM speeds even with two DDR3 UDIMM modules per channel. AM1I-A only supports a single-channel operation, with at most two DIMMs per channel, so raising these limit values is required to let it (and similar boards) run faster.
Successfully tested on AM1I-A and two Crucial BLT8G3D1869DT1TX0 UDIMMs, together with related AMD_XMP changes - also required to get a 1600MT/s with this set of modules which have only 1333MT/s at JEDEC part of SPD.
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I2a9da4e594ab3dc38b5ba87520633cbd01c9ce01 --- M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpUkb3.c 1 file changed, 6 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/44461/3
Hello build bot (Jenkins), Paul Menzel, Angel Pons, HAOUAS Elyes,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44461
to look at the new patch set (#4).
Change subject: vc/amd/agesa/f16kb: raise the UDIMM Freq limit 1333MT/s values to 1600MT/s ......................................................................
vc/amd/agesa/f16kb: raise the UDIMM Freq limit 1333MT/s values to 1600MT/s
AMD f16kb boards are perfectly capable of working at 1600MT/s RAM speeds even with two DDR3 UDIMM modules per channel. AM1I-A only supports a single-channel operation, with at most two DIMMs per channel, so raising these limit values is required to let it and similar boards run faster.
Successfully tested on AM1I-A and two Crucial BLT8G3D1869DT1TX0 UDIMMs, together with related AMD_XMP changes - also required to get a 1600MT/s with this set of modules which have only 1333MT/s at JEDEC part of SPD.
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I2a9da4e594ab3dc38b5ba87520633cbd01c9ce01 --- M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpUkb3.c 1 file changed, 6 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/44461/4
Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44461 )
Change subject: vc/amd/agesa/f16kb: raise the UDIMM Freq limit 1333MT/s values to 1600MT/s ......................................................................
Patch Set 4:
(4 comments)
https://review.coreboot.org/c/coreboot/+/44461/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44461/2//COMMIT_MSG@7 PS2, Line 7: MHz
MT/s (everywhere in the commit message)
Done
https://review.coreboot.org/c/coreboot/+/44461/2//COMMIT_MSG@10 PS2, Line 10: two DDR3 UDIMM modules
two DDR3 UDIMM modules *per channel*
Done
https://review.coreboot.org/c/coreboot/+/44461/2/src/vendorcode/amd/agesa/f1... File src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpUkb3.c:
https://review.coreboot.org/c/coreboot/+/44461/2/src/vendorcode/amd/agesa/f1... PS2, Line 96: {{_2DIMM, 2, 0, 2, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
AFAIUI (and if the comments are true, this is the frequency limit for 2 DIMMs per channel when there […]
Done
https://review.coreboot.org/c/coreboot/+/44461/2/src/vendorcode/amd/agesa/f1... PS2, Line 108: STATIC CONST PSCFG_MAXFREQ_ENTRY ROMDATA MaxFreqKBMicroSrvUDIMM6L[] = {
I'd recommend deduplicating the arrays. For another patch, though.
Ack.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44461 )
Change subject: vc/amd/agesa/f16kb: raise the UDIMM Freq limit 1333MT/s values to 1600MT/s ......................................................................
Patch Set 4: Code-Review+2
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44461 )
Change subject: vc/amd/agesa/f16kb: raise the UDIMM Freq limit 1333MT/s values to 1600MT/s ......................................................................
vc/amd/agesa/f16kb: raise the UDIMM Freq limit 1333MT/s values to 1600MT/s
AMD f16kb boards are perfectly capable of working at 1600MT/s RAM speeds even with two DDR3 UDIMM modules per channel. AM1I-A only supports a single-channel operation, with at most two DIMMs per channel, so raising these limit values is required to let it and similar boards run faster.
Successfully tested on AM1I-A and two Crucial BLT8G3D1869DT1TX0 UDIMMs, together with related AMD_XMP changes - also required to get a 1600MT/s with this set of modules which have only 1333MT/s at JEDEC part of SPD.
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I2a9da4e594ab3dc38b5ba87520633cbd01c9ce01 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44461 Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpUkb3.c 1 file changed, 6 insertions(+), 6 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpUkb3.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpUkb3.c index 7e9b64e..3bc99bf 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpUkb3.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpUkb3.c @@ -92,8 +92,8 @@ {{_2DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, {{_2DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, {{_2DIMM, 2, 2, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, - {{_2DIMM, 2, 1, 1, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, - {{_2DIMM, 2, 0, 2, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, + {{_2DIMM, 2, 1, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, + {{_2DIMM, 2, 0, 2, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, }; CONST PSC_TBL_ENTRY KBMaxFreqTblEntU6L = { {PSCFG_MAXFREQ, UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY}, @@ -111,8 +111,8 @@ {{_2DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, {{_2DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, {{_2DIMM, 2, 2, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, - {{_2DIMM, 2, 1, 1, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, - {{_2DIMM, 2, 0, 2, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, + {{_2DIMM, 2, 1, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, + {{_2DIMM, 2, 0, 2, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, }; CONST PSC_TBL_ENTRY KBMaxFreqTblEntMicroSrvU6L = { {PSCFG_MAXFREQ, UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY}, @@ -130,8 +130,8 @@ {{_2DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, {{_2DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, {{_2DIMM, 2, 2, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, - {{_2DIMM, 2, 1, 1, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, - {{_2DIMM, 2, 0, 2, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, + {{_2DIMM, 2, 1, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, + {{_2DIMM, 2, 0, 2, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, }; CONST PSC_TBL_ENTRY KBMaxFreqTblEntU4L = { {PSCFG_MAXFREQ, UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY},
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44461 )
Change subject: vc/amd/agesa/f16kb: raise the UDIMM Freq limit 1333MT/s values to 1600MT/s ......................................................................
Patch Set 5:
Automatic boot test returned (PASS/FAIL/TOTAL): 7/1/8 "QEMU x86 q35/ich9" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/15917 "QEMU x86 q35/ich9" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/15916 "QEMU x86 i440fx/piix4" (x86_64) using payload SeaBIOS : FAIL : https://lava.9esec.io/r/15915 "QEMU x86 i440fx/piix4" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/15914 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/15913 "HP Z220 SFF Workstation" (x86_32) using payload LinuxBoot_BusyBox_kexec : SUCCESS : https://lava.9esec.io/r/15920 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/15919 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/15918
Please note: This test is under development and might not be accurate at all!
-
9elements QA (Code Review) -
Angel Pons (Code Review)
-
Mike Banon (Code Review)