Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58896 )
Change subject: ChromeOS: Add legacy mainboard_ec_running_ro() ......................................................................
ChromeOS: Add legacy mainboard_ec_running_ro()
TBD: S3 resume path case
Change-Id: I3cb95268424dc27f8c1e26b3d34eff1a7b8eab7f Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/parrot/chromeos.c M src/mainboard/google/stout/chromeos.c M src/mainboard/samsung/lumpy/chromeos.c M src/vendorcode/google/chromeos/chromeos.h M src/vendorcode/google/chromeos/gnvs.c 6 files changed, 29 insertions(+), 29 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/58896/1
diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index 356e97b..e43d442 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -61,6 +61,15 @@ return ec_rec_mode; }
+bool mainboard_ec_running_ro(void) +{ + // TODO: MLR + // The firmware read/write status is a "virtual" switch and + // will be handled elsewhere. Until then hard-code to + // read/write instead of read-only for developer mode. + return false; +} + static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AL(WP_GPIO, CROS_GPIO_DEVICE_NAME), @@ -68,12 +77,5 @@
void mainboard_chromeos_acpi_generate(void) { - // TODO: MLR - // The firmware read/write status is a "virtual" switch and - // will be handled elsewhere. Until then hard-code to - // read/write instead of read-only for developer mode. - if (CONFIG(CHROMEOS_NVS)) - chromeos_set_ecfw_rw(); - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index 03b0d47..9f4be26 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -51,7 +51,7 @@ return gpio; }
-static int parrot_ec_running_ro(void) +bool mainboard_ec_running_ro(void) { return !get_gpio(68); } @@ -63,8 +63,5 @@
void mainboard_chromeos_acpi_generate(void) { - if (CONFIG(CHROMEOS_NVS) && !parrot_ec_running_ro()) - chromeos_set_ecfw_rw(); - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index 07fdee3..ed78b37 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -47,8 +47,7 @@ * The recovery-switch is virtual on Stout and is handled via the EC. * Stout recovery mode is only valid if RTC_PWR_STS is set and the EC * indicated the recovery keys were pressed. We use a global flag for - * rec_mode to be used after RTC_POWER_STS has been cleared. This function - * is complicated by romstage support, which can't use a global variable. + * rec_mode to be used after RTC_POWER_STS has been cleared. * Note, rec_mode is the only time the EC is in RO mode, otherwise, RW. */ int get_recovery_mode_switch(void) @@ -73,6 +72,11 @@ return ec_in_rec_mode; }
+bool mainboard_ec_running_ro(void) +{ + return !!get_recovery_mode_switch(); +} + static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), @@ -81,8 +85,5 @@
void mainboard_chromeos_acpi_generate(void) { - if (CONFIG(CHROMEOS_NVS) && !get_recovery_mode_switch()) - chromeos_set_ecfw_rw(); - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index aa96153..d5e20bd 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -68,6 +68,11 @@ pci_s_write_config32(dev, SATA_SP, flags); }
+bool mainboard_ec_running_ro(void) +{ + return !ec_read(0xcb); +} + static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), @@ -75,8 +80,5 @@
void mainboard_chromeos_acpi_generate(void) { - if (CONFIG(CHROMEOS_NVS) && ec_read(0xcb)) - chromeos_set_ecfw_rw(); - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index 391f7c9..b770525 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -30,7 +30,7 @@ void cbmem_add_vpd_calibration_data(void); void chromeos_set_me_hash(u32*, int); void chromeos_set_ramoops(void *ram_oops, size_t size); -void chromeos_set_ecfw_rw(void); +bool mainboard_ec_running_ro(void); void register_chromeos_device(void);
/** diff --git a/src/vendorcode/google/chromeos/gnvs.c b/src/vendorcode/google/chromeos/gnvs.c index 7f76597..b0a1884 100644 --- a/src/vendorcode/google/chromeos/gnvs.c +++ b/src/vendorcode/google/chromeos/gnvs.c @@ -57,8 +57,13 @@ /* EC can override to ECFW_RW. */ chromeos_acpi->vbt2 = ACTIVE_ECFW_RO;
- if (CONFIG(EC_GOOGLE_CHROMEEC) && !google_ec_running_ro()) - chromeos_acpi->vbt2 = ACTIVE_ECFW_RW; + if (CONFIG(EC_GOOGLE_CHROMEEC)) { + if (!google_ec_running_ro()) + chromeos_acpi->vbt2 = ACTIVE_ECFW_RW; + } else { + if (!mainboard_ec_running_ro()) + chromeos_acpi->vbt2 = ACTIVE_ECFW_RW; + } }
void chromeos_set_me_hash(u32 *hash, int len) @@ -81,13 +86,6 @@ chromeos_acpi->ramoops_len = size; }
-void chromeos_set_ecfw_rw(void) -{ - if (!chromeos_acpi) - return; - chromeos_acpi->vbt2 = ACTIVE_ECFW_RW; -} - void smbios_type0_bios_version(uintptr_t address) { if (!chromeos_acpi)
-
Kyösti Mälkki (Code Review)