Change in coreboot[master]: sb/intel/bd82x6x: Use common AHCI

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37138 )

Change subject: sb/intel/bd82x6x: Use common AHCI
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sb/intel/bd82x6x: Use common AHCI

Untested.

Change-Id: I180c7f11bccfcd50340ba27cd926107765713e04
Signed-off-by: Patrick Rudolph 
---
M src/southbridge/intel/bd82x6x/Kconfig
M src/southbridge/intel/bd82x6x/sata.c
2 files changed, 4 insertions(+), 28 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/37138/1

diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig
index 1c7e9b7..0c6b348 100644
--- a/src/southbridge/intel/bd82x6x/Kconfig
+++ b/src/southbridge/intel/bd82x6x/Kconfig
@@ -24,6 +24,7 @@
 config SOUTH_BRIDGE_OPTIONS # dummy
    def_bool y
    select ACPI_INTEL_HARDWARE_SLEEP_VALUES
+	select SOUTHBRIDGE_INTEL_COMMON_AHCI
    select SOUTHBRIDGE_INTEL_COMMON_FINALIZE
    select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
    select SOUTHBRIDGE_INTEL_COMMON_SMBUS
diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c
index 3ec065f..06c0f3f 100644
--- a/src/southbridge/intel/bd82x6x/sata.c
+++ b/src/southbridge/intel/bd82x6x/sata.c
@@ -23,6 +23,7 @@
 #include <pc80/mc146818rtc.h>
 #include <acpi/sata.h>
 #include <types.h>
+#include <southbridge/intel/common/ahci.h>

#include "chip.h"
 #include "pch.h"
@@ -67,8 +68,6 @@

/* AHCI */
    if (sata_mode == 0) {
-		u8 *abar;
-
    	printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n");

/* Set Interrupt Line */
@@ -101,32 +100,8 @@
    		   ((config->sata_port_map ^ 0x3f) << 24) | 0x183);

/* Initialize AHCI memory-mapped space */
-		abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
-		printk(BIOS_DEBUG, "ABAR: %p\n", abar);
-		/* CAP (HBA Capabilities) : enable power management */
-		reg32 = read32(abar + 0x00);
-		reg32 |= 0x0c006000;  // set PSC+SSC+SALP+SSS
-		reg32 &= ~0x00020060; // clear SXS+EMS+PMS
-		/* Set ISS, if available */
-		if (config->sata_interface_speed_support)
-		{
-			reg32 &= ~0x00f00000;
-			reg32 |= (config->sata_interface_speed_support & 0x03)
-			  << 20;
-		}
-		write32(abar + 0x00, reg32);
-		/* PI (Ports implemented) */
-		write32(abar + 0x0c, config->sata_port_map);
-		(void) read32(abar + 0x0c); /* Read back 1 */
-		(void) read32(abar + 0x0c); /* Read back 2 */
-		/* CAP2 (HBA Capabilities Extended)*/
-		reg32 = read32(abar + 0x24);
-		reg32 &= ~0x00000002;
-		write32(abar + 0x24, reg32);
-		/* VSP (Vendor Specific Register */
-		reg32 = read32(abar + 0xa0);
-		reg32 &= ~0x00000005;
-		write32(abar + 0xa0, reg32);
+		sb_ahci_init(dev, config->sata_port_map, false, false,
+			     config->sata_interface_speed_support, false, 5);
    } else {
            /* IDE */
    	printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n");

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37138 )

Change subject: sb/intel/bd82x6x: Use common AHCI
......................................................................

Patch Set 3: Code-Review+1

I can test this on the Asus P8Z77-V LX2

[S] Change in coreboot[master]: sb/intel/bd82x6x: Use common AHCI

[Martin L Roth (Code Review)]

Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/37138?usp=email )

Change subject: sb/intel/bd82x6x: Use common AHCI
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Abandoned

This patch has not been touched in over 12 months. Anyone who wants to take over work on this patch, please feel free to restore it and do any work needed to get it merged. If you create a new patch based on this work, please credit the original author.