Patch set updated for coreboot: northbridge/amd/amdmct/mct_ddr3: Fix Family 10h boot failure

[Timothy Pearson]

Timothy Pearson ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12013

-gerrit

commit c2569a665b0d0abbb7e6d4bf2e1b6b07b01ce46a
Author: Timothy Pearson 
Date:   Sat Jun 27 17:52:45 2015 -0500

northbridge/amd/amdmct/mct_ddr3: Fix Family 10h boot failure

Change-Id: I5dcb333d3a5a49318fe7bddd4c386642205c343e
    Signed-off-by: Timothy Pearson 
---
 src/northbridge/amd/amdmct/mct_ddr3/mct_d.c  | 28 +++++++++++++++++++++-------
 src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c |  8 +++++++-
 2 files changed, 28 insertions(+), 8 deletions(-)

diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
index e7fee19..c8d72c6 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
@@ -1635,6 +1635,11 @@ restartinit:
    	HTMemMapInit_D(pMCTstat, pDCTstatA);	/* Map local memory into system address space.*/
    	mctHookAfterHTMap();

+		if (!is_fam15h()) {
+			printk(BIOS_DEBUG, "mctAutoInitMCT_D: CPUMemTyping_D\n");
+			CPUMemTyping_D(pMCTstat, pDCTstatA);	/* Map dram into WB/UC CPU cacheability */
+		}
+
    	printk(BIOS_DEBUG, "mctAutoInitMCT_D: mctHookAfterCPU\n");
    	mctHookAfterCPU();			/* Setup external northbridge(s) */

@@ -1658,6 +1663,11 @@ restartinit:
    	printk(BIOS_DEBUG, "mctAutoInitMCT_D: DQSTiming_D\n");
    	DQSTiming_D(pMCTstat, pDCTstatA, allow_config_restore);	/* Get Receiver Enable and DQS signal timing*/

+		if (!is_fam15h()) {
+			printk(BIOS_DEBUG, "mctAutoInitMCT_D: UMAMemTyping_D\n");
+			UMAMemTyping_D(pMCTstat, pDCTstatA);	/* Fix up for UMA sizing */
+		}
+
    	if (!allow_config_restore) {
    		printk(BIOS_DEBUG, "mctAutoInitMCT_D: :OtherTiming\n");
    		mct_OtherTiming(pMCTstat, pDCTstatA);
@@ -1678,11 +1688,13 @@ restartinit:
    		MCTMemClr_D(pMCTstat,pDCTstatA);
    	}

-		printk(BIOS_DEBUG, "mctAutoInitMCT_D: CPUMemTyping_D\n");
-		CPUMemTyping_D(pMCTstat, pDCTstatA);	/* Map dram into WB/UC CPU cacheability */
+		if (is_fam15h()) {
+			printk(BIOS_DEBUG, "mctAutoInitMCT_D: CPUMemTyping_D\n");
+			CPUMemTyping_D(pMCTstat, pDCTstatA);	/* Map dram into WB/UC CPU cacheability */

-		printk(BIOS_DEBUG, "mctAutoInitMCT_D: UMAMemTyping_D\n");
-		UMAMemTyping_D(pMCTstat, pDCTstatA);	/* Fix up for UMA sizing */
+			printk(BIOS_DEBUG, "mctAutoInitMCT_D: UMAMemTyping_D\n");
+			UMAMemTyping_D(pMCTstat, pDCTstatA);	/* Fix up for UMA sizing */
+		}

printk(BIOS_DEBUG, "mctAutoInitMCT_D: mct_ForceNBPState0_Dis_Fam15\n");
    	for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) {
@@ -6353,11 +6365,13 @@ void ProgDramMRSReg_D(struct MCTStatStruc *pMCTstat,
    	DramMRS |= 1 << 1;

dword = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x84);
-	dword |= DramMRS;
-	if (is_fam15h())
+	if (is_fam15h()) {
+		dword |= DramMRS;
    	dword &= ~0x00800003;
-	else
+	} else {
    	dword &= ~0x00fc2f8f;
+		dword |= DramMRS;
+	}
    Set_NB32_DCT(pDCTstat->dev_dct, dct, 0x84, dword);
 }

diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
index 4397eba..38991c8 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
@@ -904,9 +904,15 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat,
    		 * Flush the receiver FIFO
    		 * Write one full cache line of non-0x55/0xaa data to one of the test addresses, then read it back to flush the FIFO
    		 */
-
+			/* FIXME
+			 * This does not seem to be needed, and has a tendency to lock up the
+			 * boot process while attempting to write the test pattern.
+			 */
+#if 0
+			SetUpperFSbase(TestAddr0);
    		WriteLNTestPattern(TestAddr0 << 8, (uint8_t *)TestPattern2_D, 1);
    		mct_Read1LTestPattern_D(pMCTstat, pDCTstat, TestAddr0);
+#endif
    	}
    	MaxDelay_CH[Channel] = CTLRMaxDelay;
    }