[M] Change in coreboot[master]: soc/intel/mtl: Add sign-of-life support based on uGOP PEIM driver

[Jérémy Compostella (Code Review)]

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun Tuli.

Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/77232?usp=email )

Change subject: soc/intel/mtl: Add sign-of-life support based on uGOP PEIM driver
......................................................................

soc/intel/mtl: Add sign-of-life support based on uGOP PEIM driver

This patch introduces sign-of-life support for the following
two use-cases:
1. Memory Training in FSP-M
2. CSME update

BUG=b:279173035
TEST=If `CONFIG_UGOP_EARLY_GRAPHICS' is set to y, we observe a text
     message on screen during Memory training and CSME update.

Change-Id: I358b54c71533f3b905b68d7ac0710d2337ce451d
Signed-off-by: Jeremy Compostella 
---
M src/soc/intel/meteorlake/Kconfig
M src/soc/intel/meteorlake/romstage/Makefile.inc
M src/soc/intel/meteorlake/romstage/fsp_params.c
M src/soc/intel/meteorlake/romstage/romstage.c
A src/soc/intel/meteorlake/romstage/ux.c
A src/soc/intel/meteorlake/romstage/ux.h
6 files changed, 85 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/77232/1

diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
index 6391ed8..56b2c81 100644
--- a/src/soc/intel/meteorlake/Kconfig
+++ b/src/soc/intel/meteorlake/Kconfig
@@ -30,7 +30,9 @@
    select INTEL_DESCRIPTOR_MODE_CAPABLE
    select INTEL_GMA_ACPI
    select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
+	select INTEL_GMA_ADD_VBT if UGOP_EARLY_GRAPHICS
    select INTEL_GMA_OPREGION_2_1
+	select INTEL_TXT_LIB
    select IOAPIC
    select MICROCODE_BLOB_UNDISCLOSED
    select MP_SERVICES_PPI_V2
@@ -39,6 +41,7 @@
    select PCIE_CLOCK_CONTROL_THROUGH_P2SB
    select PLATFORM_USES_FSP2_3
    select PMC_GLOBAL_RESET_ENABLE_LOCK
+	select ROMSTAGE_VGA if UGOP_EARLY_GRAPHICS
    select SOC_INTEL_COMMON
    select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
    select SOC_INTEL_COMMON_BLOCK
@@ -190,6 +193,12 @@
    default 0x80000 if BMP_LOGO
    default 0x10000

+config GFX_GMA_DEFAULT_MMIO
+	default 0xaf000000
+
+config UGOP_FILE
+	default "3rdparty/blobs/intel/mtl/ugop.efi"
+
 # Intel recommends reserving the PCIe TBT root port resources as below:
 # - 42 buses
 # - 194 MiB Non-prefetchable memory
diff --git a/src/soc/intel/meteorlake/romstage/Makefile.inc b/src/soc/intel/meteorlake/romstage/Makefile.inc
index 99c1d2c..999241c 100644
--- a/src/soc/intel/meteorlake/romstage/Makefile.inc
+++ b/src/soc/intel/meteorlake/romstage/Makefile.inc
@@ -4,3 +4,4 @@
 romstage-y += ../../../../cpu/intel/car/romstage.c
 romstage-y += romstage.c
 romstage-y += systemagent.c
+romstage-y += ux.c
diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c
index fd634ec..ad5971f 100644
--- a/src/soc/intel/meteorlake/romstage/fsp_params.c
+++ b/src/soc/intel/meteorlake/romstage/fsp_params.c
@@ -6,6 +6,7 @@
 #include <cpu/x86/msr.h>
 #include <device/device.h>
 #include <drivers/wifi/generic/wifi.h>
+#include <elog.h>
 #include <fsp/fsp_debug_event.h>
 #include <fsp/util.h>
 #include <intelbasecode/ramtop.h>
@@ -22,6 +23,8 @@
 #include <soc/soc_info.h>
 #include <string.h>

+#include "ux.h"
+
 #define FSP_CLK_NOTUSED			0xFF
 #define FSP_CLK_LAN			0x70
 #define FSP_CLK_FREE_RUNNING		0x80
@@ -388,6 +391,16 @@
    		m_cfg->SerialDebugMrcLevel = 0;
    	}
    }
+
+	/*
+	 * If valid MRC cache data is not found, FSP should perform a memory
+	 * training. Memory training can take a while so let's inform the end
+	 * user with an on-screen text message.
+	 */
+	if (!arch_upd->NvsBufferPtr) {
+		if (ux_inform_user_of_update_operation("memory training"))
+			elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_MRC);
+	}
    config = config_of_soc();

soc_memory_init_params(m_cfg, config);
diff --git a/src/soc/intel/meteorlake/romstage/romstage.c b/src/soc/intel/meteorlake/romstage/romstage.c
index 3df480c..20efb77 100644
--- a/src/soc/intel/meteorlake/romstage/romstage.c
+++ b/src/soc/intel/meteorlake/romstage/romstage.c
@@ -3,6 +3,7 @@
 #include <arch/romstage.h>
 #include <cbmem.h>
 #include <console/console.h>
+#include <elog.h>
 #include <fsp/util.h>
 #include <intelblocks/cfg.h>
 #include <intelblocks/cse.h>
@@ -10,6 +11,7 @@
 #include <intelblocks/smbus.h>
 #include <intelblocks/thermal.h>
 #include <memory_info.h>
+#include <security/intel/txt/txt.h>
 #include <soc/intel/common/smbios.h>
 #include <soc/iomap.h>
 #include <soc/pm.h>
@@ -17,6 +19,9 @@
 #include <soc/soc_chip.h>
 #include <timestamp.h>
 #include <string.h>
+#include <ugop.h>
+
+#include "ux.h"

#define FSP_SMBIOS_MEMORY_INFO_GUID	\
 {	\
@@ -121,6 +126,18 @@
    	printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt);
 }

+void cse_fw_update_misc_oper(void)
+{
+	if (ux_inform_user_of_update_operation("CSE update"))
+		elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_CSE_SYNC);
+}
+
+void cse_board_reset(void)
+{
+	if (CONFIG(UGOP_EARLY_GRAPHICS))
+		ugop_early_graphics_exit();
+}
+
 void mainboard_romstage_entry(void)
 {
    struct chipset_power_state *ps = pmc_get_power_state();
@@ -129,6 +146,16 @@
    /* Initialize HECI interface */
    cse_init(HECI1_BASE_ADDRESS);

+	/*
+	 * Disable Intel TXT if `CPU is unsupported` or `SoC haven't selected
+	 * the config`.
+	 *
+	 * It would help to access VGA framebuffer prior calling into CSE
+	 * firmware update or FSP-M.
+	 */
+	if (!CONFIG(INTEL_TXT))
+		disable_intel_txt();
+
    if (!s3wake && CONFIG(SOC_INTEL_CSE_LITE_SKU))
    	cse_fw_sync();

@@ -153,4 +180,7 @@
    pmc_set_disb();
    if (!s3wake)
    	save_dimm_info();
+
+	if (CONFIG(UGOP_EARLY_GRAPHICS))
+		ugop_early_graphics_exit();
 }
diff --git a/src/soc/intel/meteorlake/romstage/ux.c b/src/soc/intel/meteorlake/romstage/ux.c
new file mode 100644
index 0000000..c49b712
--- /dev/null
+++ b/src/soc/intel/meteorlake/romstage/ux.c
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <pc80/vga.h>
+#include <ugop.h>
+#include <ux_locales.h>
+
+#include "ux.h"
+
+#define UX_MEMORY_TRAINING_DESC "memory_training_desc"
+
+bool ux_inform_user_of_update_operation(const char *name)
+{
+	if (!CONFIG(UGOP_EARLY_GRAPHICS) || !ugop_early_graphics_init())
+		return false;
+
+	printk(BIOS_INFO, "Informing user on-display of %s.\n", name);
+
+	const char *text = ux_locales_get_text(UX_MEMORY_TRAINING_DESC);
+	/* No localized text found; fallback to built-in English. */
+	if (!text)
+		text = "Your device is finishing an update. "
+		       "This may take 1-2 minutes.\n"
+		       "Please do not turn off your device.";
+	vga_write_text(VGA_TEXT_CENTER, VGA_TEXT_HORIZONTAL_MIDDLE,
+		       (const unsigned char *)text);
+	ux_locales_unmap();
+	return true;
+}
diff --git a/src/soc/intel/meteorlake/romstage/ux.h b/src/soc/intel/meteorlake/romstage/ux.h
new file mode 100644
index 0000000..e7e1d99
--- /dev/null
+++ b/src/soc/intel/meteorlake/romstage/ux.h
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+bool ux_inform_user_of_update_operation(const char *name);