Change in coreboot[master]: soc/inte/*/gpio; Add GPE_EN and GPE_STS register definition

[Maulik V Vaghela (Code Review)]

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak.
Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, Eric Lai,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/64088

to look at the new patch set (#2).

Change subject: soc/inte/*/gpio; Add GPE_EN and GPE_STS register definition
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soc/inte/*/gpio; Add GPE_EN and GPE_STS register definition

coreboot needs to set GPE_EN bit for the GPIOs which are wake capable
from s0ix/sleep. Due to GPIO locking mechanism, coreboot/OS will not
be able to write GPE_EN register post GPIO has been locked.

This patch adds support in SoC code to provide correct offset for
GPE_EN and GPE_STS registers to the common code.

Plan is to use this offsets to set GPE_EN bits before GPIO locking
in coreboot which will be part of subsequent CL.

BUG=b:222375516
BRANCH=firmware-brya-14505.B
TEST=Check if code compiles for Brya and correct offset values are printed.

Change-Id: I6b813b30b8b360f8eccbf539b57387310e380560
Signed-off-by: Maulik V Vaghela 
---
M src/soc/intel/alderlake/gpio.c
M src/soc/intel/alderlake/include/soc/gpio_defs.h
M src/soc/intel/cannonlake/gpio.c
M src/soc/intel/cannonlake/include/soc/gpio_defs.h
M src/soc/intel/common/block/include/intelblocks/gpio.h
M src/soc/intel/tigerlake/gpio.c
M src/soc/intel/tigerlake/include/soc/gpio_defs.h
7 files changed, 40 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/64088/2