Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48390 )
Change subject: soc/intel/cannonlake: Align SATA mode names with soc/skl ......................................................................
soc/intel/cannonlake: Align SATA mode names with soc/skl
Align the SATA mode names with soc/skl providing a consistent API.
Built clevo/l140cu with BUILD_TIMELESS=1, coreboot.rom remains identical.
Change-Id: I54b48462852d7fe0230dde0c272da3d12365d987 Signed-off-by: Felix Singer felixsinger@posteo.net Reviewed-on: https://review.coreboot.org/c/coreboot/+/48390 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Matt DeVillier matt.devillier@gmail.com Reviewed-by: Michael Niewöhner foss@mniewoehner.de --- M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb M src/mainboard/system76/lemp9/devicetree.cb M src/soc/intel/cannonlake/chip.h 7 files changed, 8 insertions(+), 8 deletions(-)
Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved Michael Niewöhner: Looks good to me, approved
diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index 3bb802e..67d35b3 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -113,7 +113,7 @@ device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 device pci 17.0 on # SATA - register "SataMode" = "Sata_AHCI" + register "SataMode" = "SATA_AHCI" register "SataSalpSupport" = "1" # Port 2 (J_SSD2) register "SataPortsEnable[1]" = "1" diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 31f6652..5826f79 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -20,7 +20,7 @@ # FSP configuration register "SkipExtGfxScan" = "1" register "SataSalpSupport" = "1" - register "SataMode" = "Sata_AHCI" + register "SataMode" = "SATA_AHCI" register "SataPortsEnable[1]" = "1" register "SataPortsDevSlp[1]" = "1" # Configure devslp pad reset to PLT_RST diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 9e05213..69e4e7d 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -16,7 +16,7 @@ # FSP configuration register "SaGv" = "SaGv_Enabled" register "SataSalpSupport" = "1" - register "SataMode" = "Sata_AHCI" + register "SataMode" = "SATA_AHCI" register "SataPortsEnable[2]" = "1" register "SataPortsDevSlp[2]" = "1" register "SkipExtGfxScan" = "1" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 005a783..021feba 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -16,7 +16,7 @@ # FSP configuration register "SaGv" = "SaGv_Enabled" register "SataSalpSupport" = "1" - register "SataMode" = "Sata_AHCI" + register "SataMode" = "SATA_AHCI" register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" register "SataPortsEnable[2]" = "1" diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb index c39bccf..571a336 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb @@ -172,7 +172,7 @@ device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 device pci 17.0 on # SATA - register "SataMode" = "Sata_AHCI" + register "SataMode" = "SATA_AHCI" register "SataPortsEnable[0]" = "1" # 2.5" register "SataPortsEnable[2]" = "1" # m.2 register "satapwroptimize" = "1" diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb index 8e45eba..1f92fec 100644 --- a/src/mainboard/system76/lemp9/devicetree.cb +++ b/src/mainboard/system76/lemp9/devicetree.cb @@ -113,7 +113,7 @@ device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 device pci 17.0 on # SATA - register "SataMode" = "Sata_AHCI" + register "SataMode" = "SATA_AHCI" register "SataSalpSupport" = "1" # Port 2 (J_SSD2) register "SataPortsEnable[1]" = "1" diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index a084f67..70aab92 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -129,8 +129,8 @@
/* SATA related */ enum { - Sata_AHCI, - Sata_RAID, + SATA_AHCI, + SATA_RAID, } SataMode;
/* SATA devslp pad reset configuration */
-
Michael Niewöhner (Code Review)