Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52785 )
Change subject: drivers/intel/fsp1_1: Remove verstage compilation units ......................................................................
drivers/intel/fsp1_1: Remove verstage compilation units
Only SOC_INTEL_BRASWELL is using FSP1.1. It has too little CAR available set up by FSP-T to have VBOOT_STARTS_IN_BOOTBLOCK and therefore verstage is not possible either.
Change-Id: I54361c835055907c2a4414ec26a1495425d4ef09 Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/coreboot/+/52785 Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Frans Hendriks fhendriks@eltan.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/drivers/intel/fsp1_1/Makefile.inc D src/drivers/intel/fsp1_1/verstage.c 2 files changed, 0 insertions(+), 15 deletions(-)
Approvals: build bot (Jenkins): Verified Frans Hendriks: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve
diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc index 4b8e0a8..c890f35 100644 --- a/src/drivers/intel/fsp1_1/Makefile.inc +++ b/src/drivers/intel/fsp1_1/Makefile.inc @@ -2,10 +2,6 @@
ifeq ($(CONFIG_PLATFORM_USES_FSP1_1),y)
-verstage-y += car.c -verstage-y += fsp_util.c -verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += verstage.c - bootblock-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += cache_as_ram.S bootblock-y += fsp_util.c bootblock-y += ../../../cpu/intel/microcode/microcode_asm.S diff --git a/src/drivers/intel/fsp1_1/verstage.c b/src/drivers/intel/fsp1_1/verstage.c deleted file mode 100644 index c001b62..0000000 --- a/src/drivers/intel/fsp1_1/verstage.c +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <fsp/car.h> -#include <program_loading.h> - -void *cache_as_ram_stage_main(FSP_INFO_HEADER *fih) -{ - run_romstage(); - /* Will actually never return. */ - return NULL; -}