[S] Change in coreboot[master]: soc/amd/phoenix/chipset.cb: add missing GPP bridges on device 1

[Felix Held (Code Review)]

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72736 )

Change subject: soc/amd/phoenix/chipset.cb: add missing GPP bridges on device 1
......................................................................

soc/amd/phoenix/chipset.cb: add missing GPP bridges on device 1

Only the PCIe ports on the functions of device 2 were present in the
devicetree and had the amd_external_pcie_gpp_ops ops assigned. Add the
missing PCIe ports on the functions of device 1 and assign the
amd_external_pcie_gpp_ops ops to them.

Signed-off-by: Felix Held 
Change-Id: Ib5c62c1df585877d9b6986a462a3636d4f2eb4c7
---
M src/soc/amd/phoenix/chipset.cb
1 file changed, 18 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/72736/1

diff --git a/src/soc/amd/phoenix/chipset.cb b/src/soc/amd/phoenix/chipset.cb
index 5c341c8..e314c39 100644
--- a/src/soc/amd/phoenix/chipset.cb
+++ b/src/soc/amd/phoenix/chipset.cb
@@ -10,6 +10,9 @@
    	device pci 00.2 alias iommu off ops amd_iommu_ops end

device pci 01.0 on end # Dummy Host Bridge
+		device pci 01.1 alias gpp_bridge_1_0 off ops amd_external_pcie_gpp_ops end
+		device pci 01.2 alias gpp_bridge_1_1 off ops amd_external_pcie_gpp_ops end
+		device pci 01.3 alias gpp_bridge_1_2 off ops amd_external_pcie_gpp_ops end

device pci 02.0 on end # Dummy Host Bridge, do not disable
    	device pci 02.1 alias gpp_bridge_0 off ops amd_external_pcie_gpp_ops end