Change in coreboot[master]: soc/amd/cezanne: Enable secure counters

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59477 )

Change subject: soc/amd/cezanne: Enable secure counters
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soc/amd/cezanne: Enable secure counters

Guybrush uses secure counters to protect against High Definition (HD)
protected content rollback. These secure counters are hosted in TPM
NVRAM. Enable secure counters so that they are defined in PSP verstage.

BUG=b:205261728
TEST=Build and boot to OS in Guybrush. Ensure that the secure counters
are defined successfully in TPM NVRAM.

Change-Id: I6818c6f7905aa2eb815059e23c4f79437593f8ca
Signed-off-by: Karthikeyan Ramasubramanian 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59477
Tested-by: build bot (Jenkins) 
Reviewed-by: Rob Barnes 
Reviewed-by: Raul Rangel 
---
M src/soc/amd/cezanne/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Raul Rangel: Looks good to me, approved
  Rob Barnes: Looks good to me, approved

diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index b4e808d..df37a82 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -72,6 +72,7 @@
    select SOC_AMD_COMMON_FSP_PCI
    select SSE2
    select UDK_2017_BINDING
+	select VBOOT_DEFINE_WIDEVINE_COUNTERS if VBOOT_STARTS_BEFORE_BOOTBLOCK
    select X86_AMD_FIXED_MTRRS
    select X86_INIT_NEED_1_SIPI

5 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.