Edward O'Callaghan (eocallaghan@alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7196
-gerrit
commit d8b507d63e21f30a3abc1ca9dcf672e2fd82d1c1 Author: Edward O'Callaghan eocallaghan@alterapraxis.com Date: Sun Oct 26 10:36:02 2014 +1100
NOTFORMERGE: fix reset.c
Change-Id: I1a1412a1ee4125dcf1f01dc1f2ec6fd43b5d3c1f Signed-off-by: Edward O'Callaghan eocallaghan@alterapraxis.com --- src/northbridge/amd/amdfam10/reset_test.c | 10 +++++----- src/northbridge/amd/amdk8/reset_test.c | 4 ++-- src/southbridge/amd/amd8111/reset.c | 14 ++++++-------- src/southbridge/broadcom/bcm5785/reset.c | 6 ++---- src/southbridge/nvidia/ck804/reset.c | 6 ++---- src/southbridge/nvidia/mcp55/reset.c | 6 ++---- src/southbridge/sis/sis966/reset.c | 6 ++---- 7 files changed, 21 insertions(+), 31 deletions(-)
diff --git a/src/northbridge/amd/amdfam10/reset_test.c b/src/northbridge/amd/amdfam10/reset_test.c index 24f5397..de7949e 100644 --- a/src/northbridge/amd/amdfam10/reset_test.c +++ b/src/northbridge/amd/amdfam10/reset_test.c @@ -32,7 +32,7 @@ u32 cpu_init_detected(u8 nodeid) { u32 htic; - device_t dev; + pci_devfn_t dev;
dev = NODE_PCI(nodeid, 0); htic = pci_io_read_config32(dev, HT_INIT_CONTROL); @@ -67,7 +67,7 @@ u32 other_reset_detected(void) // other warm reset not started by BIOS static void distinguish_cpu_resets(u8 nodeid) { u32 htic; - device_t device; + pci_devfn_t device; device = NODE_PCI(nodeid, 0); htic = pci_io_read_config32(device, HT_INIT_CONTROL); htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect; @@ -77,7 +77,7 @@ static void distinguish_cpu_resets(u8 nodeid) static u32 warm_reset_detect(u8 nodeid) { u32 htic; - device_t device; + pci_devfn_t device; device = NODE_PCI(nodeid, 0); htic = pci_io_read_config32(device, HT_INIT_CONTROL); return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect); @@ -89,7 +89,7 @@ void __attribute__ ((weak)) set_bios_reset(void)
u32 nodes; u32 htic; - device_t dev; + pci_devfn_t dev; int i;
nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; @@ -134,7 +134,7 @@ static u8 node_link_to_bus(u8 node, u8 link) // node are 6 bit, and link three b int i; int j; u32 cfg_map_dest; - device_t dev; + pci_devfn_t dev;
cfg_map_dest = (1<<7)|(1<<6)|link;
diff --git a/src/northbridge/amd/amdk8/reset_test.c b/src/northbridge/amd/amdk8/reset_test.c index 6ef3ec0..8015290 100644 --- a/src/northbridge/amd/amdk8/reset_test.c +++ b/src/northbridge/amd/amdk8/reset_test.c @@ -10,7 +10,7 @@ static inline int cpu_init_detected(unsigned nodeid) { u32 htic; - device_t dev; + pci_devfn_t dev;
dev = PCI_DEV(0, 0x18 + nodeid, 0); htic = pci_read_config32(dev, HT_INIT_CONTROL); @@ -37,7 +37,7 @@ static inline int cold_reset_detected(void) static inline void distinguish_cpu_resets(unsigned nodeid) { u32 htic; - device_t device; + pci_devfn_t device; device = PCI_DEV(0, 0x18 + nodeid, 0); htic = pci_read_config32(device, HT_INIT_CONTROL); htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect; diff --git a/src/southbridge/amd/amd8111/reset.c b/src/southbridge/amd/amd8111/reset.c index c96e898..8824550 100644 --- a/src/southbridge/amd/amd8111/reset.c +++ b/src/southbridge/amd/amd8111/reset.c @@ -10,9 +10,7 @@ #define PCI_ID(VENDOR_ID, DEVICE_ID) \ ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF))
-typedef unsigned device_t; - -static void pci_write_config8(device_t dev, unsigned where, unsigned char value) +static void pci_write_config8(pci_devfn_t dev, unsigned where, unsigned char value) { unsigned addr; addr = (dev>>4) | where; @@ -20,7 +18,7 @@ static void pci_write_config8(device_t dev, unsigned where, unsigned char value) outb(value, 0xCFC + (addr & 3)); }
-static void pci_write_config32(device_t dev, unsigned where, unsigned value) +static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) { unsigned addr; addr = (dev>>4) | where; @@ -28,7 +26,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value) outl(value, 0xCFC); }
-static unsigned pci_read_config32(device_t dev, unsigned where) +static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) { unsigned addr; addr = (dev>>4) | where; @@ -37,9 +35,9 @@ static unsigned pci_read_config32(device_t dev, unsigned where) }
#define PCI_DEV_INVALID (0xffffffffU) -static device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) +static pci_devfn_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) { - device_t dev, last; + pci_devfn_t dev, last; dev = PCI_DEV(bus, 0, 0); last = PCI_DEV(bus, 31, 7); for(; dev <= last; dev += PCI_DEV(0,0,1)) { @@ -57,7 +55,7 @@ static device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus)
void hard_reset(void) { - device_t dev; + pci_devfn_t dev; unsigned bus; unsigned node = 0; unsigned link = get_sblk(); diff --git a/src/southbridge/broadcom/bcm5785/reset.c b/src/southbridge/broadcom/bcm5785/reset.c index 51ba6ec..b34cc86 100644 --- a/src/southbridge/broadcom/bcm5785/reset.c +++ b/src/southbridge/broadcom/bcm5785/reset.c @@ -26,9 +26,7 @@ (((DEV) & 0x1F) << 15) | \ (((FN) & 0x7) << 12))
-typedef unsigned device_t; - -static void pci_write_config32(device_t dev, unsigned where, unsigned value) +static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) { unsigned addr; addr = (dev>>4) | where; @@ -36,7 +34,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value) outl(value, 0xCFC); }
-static unsigned pci_read_config32(device_t dev, unsigned where) +static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) { unsigned addr; addr = (dev>>4) | where; diff --git a/src/southbridge/nvidia/ck804/reset.c b/src/southbridge/nvidia/ck804/reset.c index a241966..53c0c40 100644 --- a/src/southbridge/nvidia/ck804/reset.c +++ b/src/southbridge/nvidia/ck804/reset.c @@ -26,9 +26,7 @@ (((DEV) & 0x1F) << 15) | \ (((FN) & 0x7) << 12))
-typedef unsigned device_t; - -static void pci_write_config32(device_t dev, unsigned where, unsigned value) +static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) { unsigned addr; addr = (dev >> 4) | where; @@ -36,7 +34,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value) outl(value, 0xCFC); }
-static unsigned pci_read_config32(device_t dev, unsigned where) +static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) { unsigned addr; addr = (dev >> 4) | where; diff --git a/src/southbridge/nvidia/mcp55/reset.c b/src/southbridge/nvidia/mcp55/reset.c index 0ec926f..520d836 100644 --- a/src/southbridge/nvidia/mcp55/reset.c +++ b/src/southbridge/nvidia/mcp55/reset.c @@ -29,9 +29,7 @@ (((DEV) & 0x1F) << 15) | \ (((FN) & 0x7) << 12))
-typedef unsigned device_t; - -static void pci_write_config32(device_t dev, unsigned where, unsigned value) +static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) { unsigned addr; addr = (dev>>4) | where; @@ -39,7 +37,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value) outl(value, 0xCFC); }
-static unsigned pci_read_config32(device_t dev, unsigned where) +static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) { unsigned addr; addr = (dev>>4) | where; diff --git a/src/southbridge/sis/sis966/reset.c b/src/southbridge/sis/sis966/reset.c index 0ec926f..520d836 100644 --- a/src/southbridge/sis/sis966/reset.c +++ b/src/southbridge/sis/sis966/reset.c @@ -29,9 +29,7 @@ (((DEV) & 0x1F) << 15) | \ (((FN) & 0x7) << 12))
-typedef unsigned device_t; - -static void pci_write_config32(device_t dev, unsigned where, unsigned value) +static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) { unsigned addr; addr = (dev>>4) | where; @@ -39,7 +37,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value) outl(value, 0xCFC); }
-static unsigned pci_read_config32(device_t dev, unsigned where) +static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) { unsigned addr; addr = (dev>>4) | where;
-
Edward O'Callaghan