Attention is currently required from: Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik.
SH Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80768?usp=email )
Change subject: mb/google/brya/var/xol: Change clock source index for NVME ......................................................................
mb/google/brya/var/xol: Change clock source index for NVME
Change ClkSrc index for NVME to 0 from 1 by refering to proto2 schematics.
BUG=b:326481458 BRANCH=firmware-brya-14505.B TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage
Change-Id: I7ea1cd7d8e16d4cee953e931d2f1829eae7d1978 Signed-off-by: Seunghwan Kim sh_.kim@samsung.corp-partner.google.com --- M src/mainboard/google/brya/variants/xol/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/80768/1
diff --git a/src/mainboard/google/brya/variants/xol/overridetree.cb b/src/mainboard/google/brya/variants/xol/overridetree.cb index f840afe..0547dca 100644 --- a/src/mainboard/google/brya/variants/xol/overridetree.cb +++ b/src/mainboard/google/brya/variants/xol/overridetree.cb @@ -261,10 +261,10 @@ end end device ref pcie4_0 on - # Enable CPU PCIE RP 1 using CLK 1 + # Enable CPU PCIE RP 1 using CLK 0 register "cpu_pcie_rp[CPU_RP(1)]" = "{ .clk_req = 1, - .clk_src = 1, + .clk_src = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" probe STORAGE STORAGE_NVME