Change in coreboot[master]: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode

[Aamir Bohra (Code Review)]

Hello build bot (Jenkins), David Guckian, Furquan Shaikh, Tim Wawrzynczak, Duncan Laurie, Rizwan Qureshi, Vanessa Eusebio, Subrata Banik, Usha P, Shreesh Chhabbi, Patrick Rudolph, Aaron Durbin,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/43494

to look at the new patch set (#6).

Change subject: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode
......................................................................

soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode

Update the COS mask calculation to accomodate the RW data as per SoC
configuration. Currently only one way is allocated for RW data and
configured for non-eviction. For earlier platform this served fine,
and could accomodate a RW data up to 256Kb. Starting TGL and JSL, the
DCACHE_RAM_SIZE is configured for 512Kb, which cannot be mapped to a
single way. Hence update the number of ways to be configured for non-
eviction as per total LLC size.

The total LLC size/ number of ways gives the way size. DCACHE_RAM_SIZE/
way size gives the number of ways that need to be configured for non-
eviction, instead of harcoding it to 1.

TGL uses MSR IA32_CR_SF_QOS_MASK_1(0x1891) and IA32_CR_SF_QOS_MASK_2(0x1892)
as COS mask selection register and hence needs to be progarmmed accordingly.

Also JSL and TGL platforms the COS mask selection is mapped to bit 32:33
of MSR IA32_PQR_ASSOC(0xC8F) and need to be updated in edx(maps 63:32)
before MSR write instead of eax(maps 31:0). This implementation corrects
that as well.

BUG=b:149273819
TEST= Boot waddledoo(JSL), hatch(CML), Volteer(TGL)with NEM enhanced
      CAR configuration.

Signed-off-by: Aamir Bohra 
Change-Id: I54e047161853bfc70516c1d607aa479e68836d04
---
M src/include/cpu/x86/msr.h
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/common/block/cpu/Kconfig
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
M src/soc/intel/denverton_ns/Kconfig
M src/soc/intel/icelake/Kconfig
M src/soc/intel/skylake/Kconfig
7 files changed, 119 insertions(+), 43 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/43494/6