Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85620?usp=email )
(
2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/rauru: Add pwrsel init in romstage ......................................................................
mb/google/rauru: Add pwrsel init in romstage
BUG=b:317009620 TEST=build pass, reg set ok, log show: PWR_SEL = 0x0 PWRSEL_CONFIG = 0x7fff
Change-Id: I37c0fb905f99491ca99f04bc5bfa6abfb1c01059 Signed-off-by: Jarried Lin jarried.lin@mediatek.corp-partner.google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/85620 Reviewed-by: Yidi Lin yidilin@google.com Reviewed-by: Yu-Ping Wu yupingso@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/rauru/romstage.c 1 file changed, 2 insertions(+), 0 deletions(-)
Approvals: Yu-Ping Wu: Looks good to me, approved build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved
diff --git a/src/mainboard/google/rauru/romstage.c b/src/mainboard/google/rauru/romstage.c index ebeedb8..b6f0d4e 100644 --- a/src/mainboard/google/rauru/romstage.c +++ b/src/mainboard/google/rauru/romstage.c @@ -3,11 +3,13 @@ #include <arch/stages.h> #include <soc/emi.h> #include <soc/irq2axi.h> +#include <soc/mtk_pwrsel.h> #include <soc/pcie.h>
void platform_romstage_main(void) { irq2axi_disable(); + pwrsel_init(); mtk_dram_init();
if (CONFIG(PCI))