Change in coreboot[master]: soc/mediatek/mt8192: Do dramc before calibration pre-settings
Hello Duan huayang,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/44706
to review the following change.
Change subject: soc/mediatek/mt8192: Do dramc before calibration pre-settings ......................................................................
soc/mediatek/mt8192: Do dramc before calibration pre-settings
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I071eca037f89a916d6cfaf5b008d64f2b4a269a9 --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/emi.c 2 files changed, 278 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/44706/1
diff --git a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c index 08f3ea4..21a5808 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c @@ -110,6 +110,273 @@ set_dqO1_pinmux_mapping(cali); }
+static u32 get_write_latency_by_mr(u8 mr_wl) +{ + u32 write_latency = 0; + + switch(mr_wl) { + case 0: + write_latency = 4; + break; + case 1: + write_latency = 6; + break; + case 2: + write_latency = 8; + break; + case 3: + write_latency = 10; + break; + case 4: + write_latency = 12; + break; + case 5: + write_latency = 14; + break; + case 6: + write_latency = 16; + break; + case 7: + write_latency = 18; + break; + default: + dramc_info("error: unexpected mr_wl:%x\n", mr_wl); + break; + } + + dramc_info("mr_wl:%x map to WriteLatency:%d\n", mr_wl, write_latency); + return write_latency; +} + +static void tx_path_algorithm(const struct ddr_cali *cali) +{ + u8 write_latency = 0, ckr = 1, wl_mr; + u8 dqs_total_ui = 0; + u8 dqs_oe_total_ui = 0; + u8 dqs_mck, dqs_ui; + u8 dqs_oe_mck, dqs_oe_ui; + u8 small_ui_to_large; + u8 tx_dq_oe_shift = 0; + + wl_mr = (cali->mr_value->mr02[get_fsp(cali)] & 0x3f) >> 3; + small_ui_to_large = get_mck2ui_div_shift(cali); + write_latency = get_write_latency_by_mr(wl_mr); + dqs_total_ui = write_latency * ckr * 2 + 1; + tx_dq_oe_shift = 3; + + dqs_oe_total_ui = dqs_total_ui - tx_dq_oe_shift; + dqs_ui = dqs_total_ui - ((dqs_total_ui >> small_ui_to_large) << small_ui_to_large); + dqs_mck = (dqs_total_ui >> small_ui_to_large); + dqs_oe_ui = dqs_oe_total_ui - ((dqs_oe_total_ui >> small_ui_to_large) + << small_ui_to_large); + dqs_oe_mck = (dqs_oe_total_ui >> small_ui_to_large); + dramc_dbg("[TX_path_calculate] write_latency=%d, DQS_TotalUI=%d\n", + write_latency, dqs_total_ui); + dramc_dbg("[TX_path_calculate] DQS = (%d,%d) DQS_OE = (%d,%d)\n", + dqs_mck, dqs_ui, dqs_oe_mck, dqs_oe_ui); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].ao.shu_selph_dqs0, + SHU_SELPH_DQS0_TXDLY_DQS0, dqs_mck, + SHU_SELPH_DQS0_TXDLY_DQS1, dqs_mck, + SHU_SELPH_DQS0_TXDLY_OEN_DQS0, dqs_oe_mck, + SHU_SELPH_DQS0_TXDLY_OEN_DQS1, dqs_oe_mck); + SET32_BITFIELDS(&ch[chn].ao.shu_selph_dqs1, + SHU_SELPH_DQS1_DLY_DQS0, dqs_ui, + SHU_SELPH_DQS1_DLY_DQS1, dqs_ui, + SHU_SELPH_DQS1_DLY_OEN_DQS0, dqs_oe_ui, + SHU_SELPH_DQS1_DLY_OEN_DQS1, dqs_oe_ui); + } +} + +void cke_fix_onoff(const struct ddr_cali *cali, u8 chn, u8 rank, int option) +{ + u8 cke_on = 0, cke_off = 0; + bool set_rank1 = (rank == RANK_MAX) && (cali->support_ranks == DUAL_RANK_DDR); + + if (option != CKE_DYNAMIC) { + cke_on = option; + cke_off = (1 - option); + } + + if (rank == RANK_0 || rank == RANK_MAX) { + SET32_BITFIELDS(&ch[chn].ao.ckectrl, + CKECTRL_CKEFIXOFF, cke_off, + CKECTRL_CKEFIXON, cke_on); + } + if (rank == RANK_1 || set_rank1) { + SET32_BITFIELDS(&ch[chn].ao.ckectrl, + CKECTRL_CKE1FIXOFF, cke_off, + CKECTRL_CKE1FIXON, cke_on); + } +} + +static void set_cke2rank_independent(void) +{ + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].ao.rkcfg, RKCFG_CKE2RANK, 0); + SET32_BITFIELDS(&ch[chn].ao.ckectrl, + CKECTRL_CKE2RANK_OPT3, 0, + CKECTRL_CKE2RANK_OPT, 0, + CKECTRL_CKE2RANK_OPT2, 1, + CKECTRL_CKE2RANK_OPT5, 0, + CKECTRL_CKE2RANK_OPT6, 0, + CKECTRL_CKE2RANK_OPT7, 1, + CKECTRL_CKE2RANK_OPT8, 0, + CKECTRL_CKETIMER_SEL, 0, + CKECTRL_FASTWAKE_SEL, 1, + CKECTRL_CKEWAKE_SEL, 0); + SET32_BITFIELDS(&ch[chn].ao.shu_dcm_ctrl0, + SHU_DCM_CTRL0_FASTWAKE, 1, + SHU_DCM_CTRL0_FASTWAKE2, 1); + SET32_BITFIELDS(&ch[chn].ao.actiming_ctrl, ACTIMING_CTRL_CLKWITRFC, 0); + } +} + +static void dramc_hw_gating_onoff(bool is_on) +{ + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.misc_dvfsctl2, + MISC_DVFSCTL2_R_DVFS_OPTION, is_on, + MISC_DVFSCTL2_R_DVFS_PARK_N, is_on); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_stbcal2, + MISC_STBCAL2_STB_GERRSTOP, is_on); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_stbcal, + MISC_SHU_STBCAL_STBCALEN, is_on); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_stbcal, + MISC_SHU_STBCAL_STB_SELPHCALEN, is_on); + } +} + +static void dramc_reset_delay_chain_before_calibration(void) +{ + u32 bc_bak = dramc_get_broadcast(); + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + + for (u8 rk = RANK_0; rk < RANK_MAX; rk++) { + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.ca_rk[rk].shu_r0_ca_txdly0, + SHU_R0_CA_TXDLY0_TX_ARCA0_DLY, 0, + SHU_R0_CA_TXDLY0_TX_ARCA1_DLY, 0, + SHU_R0_CA_TXDLY0_TX_ARCA2_DLY, 0, + SHU_R0_CA_TXDLY0_TX_ARCA3_DLY, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.ca_rk[rk].shu_r0_ca_txdly1, + SHU_R0_CA_TXDLY1_TX_ARCA4_DLY, 0, + SHU_R0_CA_TXDLY1_TX_ARCA5_DLY, 0, + SHU_R0_CA_TXDLY1_TX_ARCA6_DLY, 0, + SHU_R0_CA_TXDLY1_TX_ARCA7_DLY, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].rk[rk].shu_r0_b0_txdly0, + SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0, 0, + SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0, 0, + SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0, 0, + SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].rk[rk].shu_r0_b0_txdly1, + SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0, 0, + SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0, 0, + SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0, 0, + SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].rk[rk].shu_r0_b0_txdly0, + SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1, 0, + SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1, 0, + SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1, 0, + SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].rk[rk].shu_r0_b0_txdly1, + SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1, 0, + SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1, 0, + SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1, 0, + SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].rk[rk].shu_r0_b0_txdly3, + SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0, 0x0); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].rk[rk].shu_r0_b0_txdly3, + SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1, 0x0); + } + } + + dramc_set_broadcast(bc_bak); +} + +static void dramc_init(const struct ddr_cali *cali) +{ + dramc_reset_delay_chain_before_calibration(); +} + +static void dramc_before_calibration(const struct ddr_cali *cali) +{ + u8 ma_type = get_column_num(); + dram_freq_grp freq_group = cali->freq_group; + u8 dis_imp_hw = (freq_group > DDRFREQ_1200) ? 0: 1; + + dramc_hw_gating_onoff(false); + + cke_fix_onoff(cali, CHANNEL_A, RANK_MAX, CKE_FIXON); + cke_fix_onoff(cali, CHANNEL_B, RANK_MAX, CKE_FIXON); + + set_cke2rank_independent(); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].ao.shu_tx_set0, SHU_TX_SET0_DBIWR, 0x0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_impedamce_upd_dis1, + MISC_SHU_IMPEDAMCE_UPD_DIS1_ODTN_UPD_DIS, dis_imp_hw, + MISC_SHU_IMPEDAMCE_UPD_DIS1_DRVN_UPD_DIS, dis_imp_hw, + MISC_SHU_IMPEDAMCE_UPD_DIS1_DRVP_UPD_DIS, dis_imp_hw, + MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_ODTN_UPD_DIS, dis_imp_hw, + MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVN_UPD_DIS, dis_imp_hw, + MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVP_UPD_DIS, dis_imp_hw, + MISC_SHU_IMPEDAMCE_UPD_DIS1_DQ_ODTN_UPD_DIS, dis_imp_hw, + MISC_SHU_IMPEDAMCE_UPD_DIS1_DQ_DRVN_UPD_DIS, dis_imp_hw, + MISC_SHU_IMPEDAMCE_UPD_DIS1_DQ_DRVP_UPD_DIS, dis_imp_hw, + MISC_SHU_IMPEDAMCE_UPD_DIS1_DQS_ODTN_UPD_DIS, dis_imp_hw, + MISC_SHU_IMPEDAMCE_UPD_DIS1_DQS_DRVN_UPD_DIS, dis_imp_hw, + MISC_SHU_IMPEDAMCE_UPD_DIS1_DQS_DRVP_UPD_DIS, dis_imp_hw, + MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVP_UPD_DIS, 1, + MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVN_UPD_DIS, 1, + MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_ODTN_UPD_DIS, 1); + + SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_impcal1, + SHU_MISC_IMPCAL1_IMPCALCNT, (dis_imp_hw? 0x0:0x40)); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_drving1, + SHU_MISC_DRVING1_DIS_IMPCAL_HW, dis_imp_hw); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_drving1, + SHU_MISC_DRVING1_DIS_IMP_ODTN_TRACK, dis_imp_hw); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_drving2, + SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN, dis_imp_hw); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd12, + SHU_CA_CMD12_RG_RIMP_UNTERM_EN, dis_imp_hw); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_clk_ctrl, + MISC_CLK_CTRL_DVFS_CLK_MEM_SEL, 0, + MISC_CLK_CTRL_DVFS_MEM_CK_MUX_UPDATE_EN, 0); + SET32_BITFIELDS(&ch[chn].ao.shu_zq_set0, + SHU_ZQ_SET0_ZQCSCNT, 0x1ff, + SHU_ZQ_SET0_TZQLAT, 0x1b); + SET32_BITFIELDS(&ch[chn].ao.zq_set0, + ZQ_SET0_ZQCSDUAL, 1, + ZQ_SET0_ZQCSMASK_OPT, 0, + ZQ_SET0_ZQMASK_CGAR, 0, + ZQ_SET0_ZQCS_MASK_SEL_CGAR, 0); + } + SET32_BITFIELDS(&ch[0].ao.zq_set0, ZQ_SET0_ZQCSMASK, 1); + SET32_BITFIELDS(&ch[1].ao.zq_set0, ZQ_SET0_ZQCSMASK, 0); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].ao.zq_set0, ZQ_SET0_ZQCS_MASK_SEL, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq2, + SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq2, + SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1, 0); + SET32_BITFIELDS(&ch[chn].ao.dcm_sub_ctrl, + DCM_SUB_CTRL_SUBCLK_CTRL_TX_AUTOK, 0x0); + SET32_BITFIELDS(&ch[chn].ao.dcm_sub_ctrl, + DCM_SUB_CTRL_SUBCLK_CTRL_TX_TRACKING, 0); + SET32_BITFIELDS(&ch[chn].ao.dqsoscr, DQSOSCR_DQSOSCRDIS, 0x1); + SET32_BITFIELDS(&ch[chn].ao.refctrl0, REFCTRL0_REFDIS, 0x1); + SET32_BITFIELDS(&ch[chn].ao.shu_matype, SHU_MATYPE_MATYPE, ma_type); + } + tx_path_algorithm(cali); +} + void dfs_init_for_calibration(const struct ddr_cali *cali) { + dramc_init(cali); + dramc_before_calibration(cali); } + diff --git a/src/soc/mediatek/mt8192/emi.c b/src/soc/mediatek/mt8192/emi.c index eb110cc..b587993 100644 --- a/src/soc/mediatek/mt8192/emi.c +++ b/src/soc/mediatek/mt8192/emi.c @@ -309,6 +309,17 @@ write32(&ch[chn].emi_chn.cona, emi_con->chn_cona_val); }
+u32 get_column_num(void) +{ + u32 ma_type = read32(&emi_reg->cona); + u32 ma_type_r0 = ((ma_type >> 20) & 0x3) + 1; + u32 ma_type_r1 = ((ma_type >> 22) & 0x3) + 1; + + ma_type = (ma_type_r0 > ma_type_r1) ? ma_type_r1 : ma_type_r0; + + return ma_type; +} + static void emi_sw_setting(void) { setbits32(&emi_mpu->mpu_ctrl_d[1], BIT(4));
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44706 )
Change subject: soc/mediatek/mt8192: Do dramc before calibration pre-settings ......................................................................
Patch Set 1:
(3 comments)
https://review.coreboot.org/c/coreboot/+/44706/1/src/soc/mediatek/mt8192/dra... File src/soc/mediatek/mt8192/dramc_pi_basic_api.c:
https://review.coreboot.org/c/coreboot/+/44706/1/src/soc/mediatek/mt8192/dra... PS1, Line 117: switch(mr_wl) { space required before the open parenthesis '('
https://review.coreboot.org/c/coreboot/+/44706/1/src/soc/mediatek/mt8192/dra... PS1, Line 307: u8 dis_imp_hw = (freq_group > DDRFREQ_1200) ? 0: 1; spaces required around that ':' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/44706/1/src/soc/mediatek/mt8192/dra... PS1, Line 336: SHU_MISC_IMPCAL1_IMPCALCNT, (dis_imp_hw? 0x0:0x40)); spaces required around that '?' (ctx:VxW)
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44706 )
Change subject: soc/mediatek/mt8192: Do dramc before calibration pre-settings ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44706/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44706/1//COMMIT_MSG@8 PS1, Line 8: Please add the reasoning for this change to the commit message.
Hello build bot (Jenkins), Julius Werner, Duan huayang,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44706
to look at the new patch set (#2).
Change subject: soc/mediatek/mt8192: Do dramc before calibration pre-settings ......................................................................
soc/mediatek/mt8192: Do dramc before calibration pre-settings
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I071eca037f89a916d6cfaf5b008d64f2b4a269a9 --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/emi.c 2 files changed, 278 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/44706/2
Yidi Lin has uploaded a new patch set (#24) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44706 )
Change subject: soc/mediatek/mt8192: Do dramc before calibration pre-settings ......................................................................
soc/mediatek/mt8192: Do dramc before calibration pre-settings
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I071eca037f89a916d6cfaf5b008d64f2b4a269a9 --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/emi.c 2 files changed, 278 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/44706/24
Yidi Lin has uploaded a new patch set (#34) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44706 )
Change subject: soc/mediatek/mt8192: Do dramc before calibration pre-settings ......................................................................
soc/mediatek/mt8192: Do dramc before calibration pre-settings
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I071eca037f89a916d6cfaf5b008d64f2b4a269a9 --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/emi.c 2 files changed, 278 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/44706/34
Yidi Lin has uploaded a new patch set (#36) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44706 )
Change subject: soc/mediatek/mt8192: Do dramc before calibration pre-settings ......................................................................
soc/mediatek/mt8192: Do dramc before calibration pre-settings
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I071eca037f89a916d6cfaf5b008d64f2b4a269a9 --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/emi.c 2 files changed, 278 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/44706/36
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44706 )
Change subject: soc/mediatek/mt8192: Do dramc before calibration pre-settings ......................................................................
Patch Set 36:
src/soc/mediatek/mt8192/dramc_pi_basic_api.c has multiple final newlines.
Xi Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44706 )
Change subject: soc/mediatek/mt8192: Do dramc before calibration pre-settings ......................................................................
Patch Set 36:
Patch Set 36:
src/soc/mediatek/mt8192/dramc_pi_basic_api.c has multiple final newlines.
sorry for that what does the multiple final newlines mean? I saw one more newline in the end of the file, and contains other newlines?
Xi Chen has uploaded a new patch set (#37) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44706 )
Change subject: soc/mediatek/mt8192: Do dramc pre-settings before calibration ......................................................................
soc/mediatek/mt8192: Do dramc pre-settings before calibration
Before calibration, dramc resets the delay of each PHY IO, calculates TX path, set CKE to rank independent.
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I071eca037f89a916d6cfaf5b008d64f2b4a269a9 --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/emi.c 2 files changed, 277 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/44706/37
Xi Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44706 )
Change subject: soc/mediatek/mt8192: Do dramc pre-settings before calibration ......................................................................
Patch Set 37:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44706/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44706/1//COMMIT_MSG@8 PS1, Line 8:
Please add the reasoning for this change to the commit message.
Done
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44706 )
Change subject: soc/mediatek/mt8192: Do dramc pre-settings before calibration ......................................................................
Patch Set 37:
sorry for that what does the multiple final newlines mean? I saw one more newline in the end of the file, and contains other newlines?
You already fixed it. We should not leave extra blank lines in end of files.
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44706 )
Change subject: soc/mediatek/mt8192: Do dramc pre-settings before calibration ......................................................................
Patch Set 41:
(13 comments)
https://review.coreboot.org/c/coreboot/+/44706/41//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44706/41//COMMIT_MSG@10 PS41, Line 10: set and sets
https://review.coreboot.org/c/coreboot/+/44706/41//COMMIT_MSG@10 PS41, Line 10: to to be
https://review.coreboot.org/c/coreboot/+/44706/41/src/soc/mediatek/mt8192/dr... File src/soc/mediatek/mt8192/dramc_pi_basic_api.c:
https://review.coreboot.org/c/coreboot/+/44706/41/src/soc/mediatek/mt8192/dr... PS41, Line 141: : A space after ":"
https://review.coreboot.org/c/coreboot/+/44706/41/src/soc/mediatek/mt8192/dr... PS41, Line 141: dramc_info dramc_err
https://review.coreboot.org/c/coreboot/+/44706/41/src/soc/mediatek/mt8192/dr... PS41, Line 142: break; return 0 here
https://review.coreboot.org/c/coreboot/+/44706/41/src/soc/mediatek/mt8192/dr... PS41, Line 145: : A space after ":"
https://review.coreboot.org/c/coreboot/+/44706/41/src/soc/mediatek/mt8192/dr... PS41, Line 145: : A space after ":"
https://review.coreboot.org/c/coreboot/+/44706/41/src/soc/mediatek/mt8192/dr... PS41, Line 151: = 0 No need to initialize. Same for dqs_total_ui, dqs_oe_total_ui.
https://review.coreboot.org/c/coreboot/+/44706/41/src/soc/mediatek/mt8192/dr... PS41, Line 151: ckr const u8 ckr = 1;
https://review.coreboot.org/c/coreboot/+/44706/41/src/soc/mediatek/mt8192/dr... PS41, Line 157: u8 tx_dq_oe_shift = 0; const tx_dq_oe_shift = 3;
https://review.coreboot.org/c/coreboot/+/44706/41/src/soc/mediatek/mt8192/dr... PS41, Line 171: d u. Same below.
https://review.coreboot.org/c/coreboot/+/44706/41/src/soc/mediatek/mt8192/dr... PS41, Line 197: ( No need for parentheses.
https://review.coreboot.org/c/coreboot/+/44706/41/src/soc/mediatek/mt8192/dr... PS41, Line 256: &ch[chn].phy_ao Since this is repeated many times, could you define a const pointer for it?
Yidi Lin has uploaded a new patch set (#43) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44706 )
Change subject: soc/mediatek/mt8192: Do dramc pre-settings before calibration ......................................................................
soc/mediatek/mt8192: Do dramc pre-settings before calibration
Before calibration, dramc resets the delay of each PHY IO, calculates TX path, set CKE to rank independent.
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I071eca037f89a916d6cfaf5b008d64f2b4a269a9 --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/emi.c 2 files changed, 277 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/44706/43
Xi Chen has uploaded a new patch set (#44) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44706 )
Change subject: soc/mediatek/mt8192: Do dramc pre-settings before calibration ......................................................................
soc/mediatek/mt8192: Do dramc pre-settings before calibration
Before calibration, dramc resets the delay of each PHY IO, calculates TX path and sets CKE to be rank independent.
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I071eca037f89a916d6cfaf5b008d64f2b4a269a9 --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/emi.c 2 files changed, 279 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/44706/44
Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44706 )
Change subject: soc/mediatek/mt8192: Do dramc pre-settings before calibration ......................................................................
Patch Set 44:
(13 comments)
https://review.coreboot.org/c/coreboot/+/44706/41//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44706/41//COMMIT_MSG@10 PS41, Line 10: set
and sets
Done
https://review.coreboot.org/c/coreboot/+/44706/41//COMMIT_MSG@10 PS41, Line 10: to
to be
Done
https://review.coreboot.org/c/coreboot/+/44706/41/src/soc/mediatek/mt8192/dr... File src/soc/mediatek/mt8192/dramc_pi_basic_api.c:
https://review.coreboot.org/c/coreboot/+/44706/41/src/soc/mediatek/mt8192/dr... PS41, Line 141: :
A space after ":"
Done
https://review.coreboot.org/c/coreboot/+/44706/41/src/soc/mediatek/mt8192/dr... PS41, Line 141: dramc_info
dramc_err
Done
https://review.coreboot.org/c/coreboot/+/44706/41/src/soc/mediatek/mt8192/dr... PS41, Line 142: break;
return 0 here
Done
https://review.coreboot.org/c/coreboot/+/44706/41/src/soc/mediatek/mt8192/dr... PS41, Line 145: :
A space after ":"
Done
https://review.coreboot.org/c/coreboot/+/44706/41/src/soc/mediatek/mt8192/dr... PS41, Line 145: :
A space after ":"
Done
https://review.coreboot.org/c/coreboot/+/44706/41/src/soc/mediatek/mt8192/dr... PS41, Line 151: ckr
const u8 ckr = 1;
Done
https://review.coreboot.org/c/coreboot/+/44706/41/src/soc/mediatek/mt8192/dr... PS41, Line 151: = 0
No need to initialize. Same for dqs_total_ui, dqs_oe_total_ui.
Done
https://review.coreboot.org/c/coreboot/+/44706/41/src/soc/mediatek/mt8192/dr... PS41, Line 157: u8 tx_dq_oe_shift = 0;
const tx_dq_oe_shift = 3;
Done
https://review.coreboot.org/c/coreboot/+/44706/41/src/soc/mediatek/mt8192/dr... PS41, Line 171: d
u. Same below.
Done
https://review.coreboot.org/c/coreboot/+/44706/41/src/soc/mediatek/mt8192/dr... PS41, Line 197: (
No need for parentheses.
Done
https://review.coreboot.org/c/coreboot/+/44706/41/src/soc/mediatek/mt8192/dr... PS41, Line 256: &ch[chn].phy_ao
Since this is repeated many times, could you define a const pointer for it?
Done
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44706 )
Change subject: soc/mediatek/mt8192: Do dramc pre-settings before calibration ......................................................................
Patch Set 44:
(5 comments)
https://review.coreboot.org/c/coreboot/+/44706/44/src/soc/mediatek/mt8192/dr... File src/soc/mediatek/mt8192/dramc_pi_basic_api.c:
https://review.coreboot.org/c/coreboot/+/44706/44/src/soc/mediatek/mt8192/dr... PS44, Line 116: case 0: : write_latency = 4; : break; : case 1: : write_latency = 6; : break; : case 2: : write_latency = 8; : break; : case 3: : write_latency = 10; : break; : case 4: : write_latency = 12; : break; : case 5: : write_latency = 14; : break; : case 6: : write_latency = 16; : break; : case 7: : write_latency = 18; : break; Is the following the right logic?
write_latency = mr_wl * 2 + 4;
https://review.coreboot.org/c/coreboot/+/44706/44/src/soc/mediatek/mt8192/dr... PS44, Line 157: small_ui_to_large Can we name it 'shift'?
https://review.coreboot.org/c/coreboot/+/44706/44/src/soc/mediatek/mt8192/dr... PS44, Line 167: ( No parentheses.
https://review.coreboot.org/c/coreboot/+/44706/44/src/soc/mediatek/mt8192/dr... PS44, Line 170: ( No parentheses.
https://review.coreboot.org/c/coreboot/+/44706/44/src/soc/mediatek/mt8192/em... File src/soc/mediatek/mt8192/emi.c:
https://review.coreboot.org/c/coreboot/+/44706/44/src/soc/mediatek/mt8192/em... PS44, Line 323: ma_type = (ma_type_r0 > ma_type_r1) ? ma_type_r1 : ma_type_r0; : : return ma_type; return MIN(ma_type_r0, ma_type_r1)
Xi Chen has uploaded a new patch set (#45) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44706 )
Change subject: soc/mediatek/mt8192: Do dramc pre-settings before calibration ......................................................................
soc/mediatek/mt8192: Do dramc pre-settings before calibration
Before calibration, dramc resets the delay of each PHY IO, calculates TX path and sets CKE to be rank independent.
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I071eca037f89a916d6cfaf5b008d64f2b4a269a9 --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/emi.c 2 files changed, 279 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/44706/45
Xi Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44706 )
Change subject: soc/mediatek/mt8192: Do dramc pre-settings before calibration ......................................................................
Patch Set 44:
(4 comments)
https://review.coreboot.org/c/coreboot/+/44706/44/src/soc/mediatek/mt8192/dr... File src/soc/mediatek/mt8192/dramc_pi_basic_api.c:
https://review.coreboot.org/c/coreboot/+/44706/44/src/soc/mediatek/mt8192/dr... PS44, Line 116: case 0: : write_latency = 4; : break; : case 1: : write_latency = 6; : break; : case 2: : write_latency = 8; : break; : case 3: : write_latency = 10; : break; : case 4: : write_latency = 12; : break; : case 5: : write_latency = 14; : break; : case 6: : write_latency = 16; : break; : case 7: : write_latency = 18; : break;
Is the following the right logic? […]
The values are from JEDEC LPDDR4 spec. " For x16 mode WL Set "A” (MR2 OP[6]=0B) 000B: WL=4 (Default) 001B: WL=6 010B: WL=8 011B: WL=10 100B: WL=12 101B: WL=14 110B: WL=16 111B: WL=18 " Your formula result is right, but the SPEC doesn't mean that it's calculated by mr_wl * 2 + 4, so can we just follow the spec literal settings?
https://review.coreboot.org/c/coreboot/+/44706/44/src/soc/mediatek/mt8192/dr... PS44, Line 157: small_ui_to_large
Can we name it 'shift'?
Ack
https://review.coreboot.org/c/coreboot/+/44706/44/src/soc/mediatek/mt8192/dr... PS44, Line 167: (
No parentheses.
Ack
https://review.coreboot.org/c/coreboot/+/44706/44/src/soc/mediatek/mt8192/dr... PS44, Line 170: (
No parentheses.
Ack
Xi Chen has uploaded a new patch set (#46) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44706 )
Change subject: soc/mediatek/mt8192: Do dramc pre-settings before calibration ......................................................................
soc/mediatek/mt8192: Do dramc pre-settings before calibration
Before calibration, dramc resets the delay of each PHY IO, calculates TX path and sets CKE to be rank independent.
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I071eca037f89a916d6cfaf5b008d64f2b4a269a9 --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/emi.c 2 files changed, 279 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/44706/46
Xi Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44706 )
Change subject: soc/mediatek/mt8192: Do dramc pre-settings before calibration ......................................................................
Patch Set 46:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44706/44/src/soc/mediatek/mt8192/em... File src/soc/mediatek/mt8192/emi.c:
https://review.coreboot.org/c/coreboot/+/44706/44/src/soc/mediatek/mt8192/em... PS44, Line 323: ma_type = (ma_type_r0 > ma_type_r1) ? ma_type_r1 : ma_type_r0; : : return ma_type;
return MIN(ma_type_r0, ma_type_r1)
Ack
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44706 )
Change subject: soc/mediatek/mt8192: Do dramc pre-settings before calibration ......................................................................
Patch Set 46:
(2 comments)
https://review.coreboot.org/c/coreboot/+/44706/44/src/soc/mediatek/mt8192/dr... File src/soc/mediatek/mt8192/dramc_pi_basic_api.c:
https://review.coreboot.org/c/coreboot/+/44706/44/src/soc/mediatek/mt8192/dr... PS44, Line 116: case 0: : write_latency = 4; : break; : case 1: : write_latency = 6; : break; : case 2: : write_latency = 8; : break; : case 3: : write_latency = 10; : break; : case 4: : write_latency = 12; : break; : case 5: : write_latency = 14; : break; : case 6: : write_latency = 16; : break; : case 7: : write_latency = 18; : break;
The values are from JEDEC LPDDR4 spec. […]
Sure.
https://review.coreboot.org/c/coreboot/+/44706/46/src/soc/mediatek/mt8192/dr... File src/soc/mediatek/mt8192/dramc_pi_basic_api.c:
https://review.coreboot.org/c/coreboot/+/44706/46/src/soc/mediatek/mt8192/dr... PS46, Line 169: << shift); Can fit into previous line. That's why I prefer a shorter name. 😊
Xi Chen has uploaded a new patch set (#47) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44706 )
Change subject: soc/mediatek/mt8192: Do dramc pre-settings before calibration ......................................................................
soc/mediatek/mt8192: Do dramc pre-settings before calibration
Before calibration, dramc resets the delay of each PHY IO, calculates TX path and sets CKE to be rank independent.
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I071eca037f89a916d6cfaf5b008d64f2b4a269a9 --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/emi.c 2 files changed, 278 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/44706/47
Xi Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44706 )
Change subject: soc/mediatek/mt8192: Do dramc pre-settings before calibration ......................................................................
Patch Set 47:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44706/46/src/soc/mediatek/mt8192/dr... File src/soc/mediatek/mt8192/dramc_pi_basic_api.c:
https://review.coreboot.org/c/coreboot/+/44706/46/src/soc/mediatek/mt8192/dr... PS46, Line 169: << shift);
Can fit into previous line. That's why I prefer a shorter name. […]
Ack
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44706 )
Change subject: soc/mediatek/mt8192: Do dramc pre-settings before calibration ......................................................................
Patch Set 47: Code-Review+2
Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44706 )
Change subject: soc/mediatek/mt8192: Do dramc pre-settings before calibration ......................................................................
soc/mediatek/mt8192: Do dramc pre-settings before calibration
Before calibration, dramc resets the delay of each PHY IO, calculates TX path and sets CKE to be rank independent.
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I071eca037f89a916d6cfaf5b008d64f2b4a269a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44706 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Yu-Ping Wu yupingso@google.com --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/emi.c 2 files changed, 278 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved
diff --git a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c index 1dae23b..719c64b 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c @@ -108,6 +108,273 @@ set_dqo1_pinmux_mapping(cali); }
+static u32 get_write_latency_by_mr(u8 mr_wl) +{ + u32 write_latency; + + switch (mr_wl) { + case 0: + write_latency = 4; + break; + case 1: + write_latency = 6; + break; + case 2: + write_latency = 8; + break; + case 3: + write_latency = 10; + break; + case 4: + write_latency = 12; + break; + case 5: + write_latency = 14; + break; + case 6: + write_latency = 16; + break; + case 7: + write_latency = 18; + break; + default: + dramc_err("error: unexpected mr_wl: %x\n", mr_wl); + return 0; + } + + dramc_info("mr_wl: %x map to WriteLatency: %d\n", mr_wl, write_latency); + return write_latency; +} + +static void tx_path_algorithm(const struct ddr_cali *cali) +{ + u8 write_latency, wl_mr; + const u8 ckr = 1; + u8 dqs_total_ui; + u8 dqs_oe_total_ui; + u8 dqs_mck, dqs_ui; + u8 dqs_oe_mck, dqs_oe_ui; + u8 shift; + const u8 tx_dq_oe_shift = 3; + + wl_mr = (cali->mr_value->mr02[get_fsp(cali)] & 0x3f) >> 3; + shift = get_mck2ui_div_shift(cali); + write_latency = get_write_latency_by_mr(wl_mr); + dqs_total_ui = write_latency * ckr * 2 + 1; + + dqs_oe_total_ui = dqs_total_ui - tx_dq_oe_shift; + dqs_ui = dqs_total_ui - ((dqs_total_ui >> shift) << shift); + dqs_mck = dqs_total_ui >> shift; + dqs_oe_ui = dqs_oe_total_ui - ((dqs_oe_total_ui >> shift) << shift); + dqs_oe_mck = dqs_oe_total_ui >> shift; + dramc_dbg("[TX_path_calculate] write_latency=%u, DQS_TotalUI=%u\n", + write_latency, dqs_total_ui); + dramc_dbg("[TX_path_calculate] DQS = (%u,%u) DQS_OE = (%u,%u)\n", + dqs_mck, dqs_ui, dqs_oe_mck, dqs_oe_ui); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].ao.shu_selph_dqs0, + SHU_SELPH_DQS0_TXDLY_DQS0, dqs_mck, + SHU_SELPH_DQS0_TXDLY_DQS1, dqs_mck, + SHU_SELPH_DQS0_TXDLY_OEN_DQS0, dqs_oe_mck, + SHU_SELPH_DQS0_TXDLY_OEN_DQS1, dqs_oe_mck); + SET32_BITFIELDS(&ch[chn].ao.shu_selph_dqs1, + SHU_SELPH_DQS1_DLY_DQS0, dqs_ui, + SHU_SELPH_DQS1_DLY_DQS1, dqs_ui, + SHU_SELPH_DQS1_DLY_OEN_DQS0, dqs_oe_ui, + SHU_SELPH_DQS1_DLY_OEN_DQS1, dqs_oe_ui); + } +} + +void cke_fix_onoff(const struct ddr_cali *cali, u8 chn, u8 rank, int option) +{ + u8 cke_on = 0, cke_off = 0; + bool set_rank1 = (rank == RANK_MAX) && (cali->support_ranks == DUAL_RANK_DDR); + + if (option != CKE_DYNAMIC) { + cke_on = option; + cke_off = 1 - option; + } + + if (rank == RANK_0 || rank == RANK_MAX) { + SET32_BITFIELDS(&ch[chn].ao.ckectrl, + CKECTRL_CKEFIXOFF, cke_off, + CKECTRL_CKEFIXON, cke_on); + } + if (rank == RANK_1 || set_rank1) { + SET32_BITFIELDS(&ch[chn].ao.ckectrl, + CKECTRL_CKE1FIXOFF, cke_off, + CKECTRL_CKE1FIXON, cke_on); + } +} + +static void set_cke2rank_independent(void) +{ + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].ao.rkcfg, RKCFG_CKE2RANK, 0); + SET32_BITFIELDS(&ch[chn].ao.ckectrl, + CKECTRL_CKE2RANK_OPT3, 0, + CKECTRL_CKE2RANK_OPT, 0, + CKECTRL_CKE2RANK_OPT2, 1, + CKECTRL_CKE2RANK_OPT5, 0, + CKECTRL_CKE2RANK_OPT6, 0, + CKECTRL_CKE2RANK_OPT7, 1, + CKECTRL_CKE2RANK_OPT8, 0, + CKECTRL_CKETIMER_SEL, 0, + CKECTRL_FASTWAKE_SEL, 1, + CKECTRL_CKEWAKE_SEL, 0); + SET32_BITFIELDS(&ch[chn].ao.shu_dcm_ctrl0, + SHU_DCM_CTRL0_FASTWAKE, 1, + SHU_DCM_CTRL0_FASTWAKE2, 1); + SET32_BITFIELDS(&ch[chn].ao.actiming_ctrl, ACTIMING_CTRL_CLKWITRFC, 0); + } +} + +static void dramc_hw_gating_onoff(bool is_on) +{ + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.misc_dvfsctl2, + MISC_DVFSCTL2_R_DVFS_OPTION, is_on, + MISC_DVFSCTL2_R_DVFS_PARK_N, is_on); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_stbcal2, + MISC_STBCAL2_STB_GERRSTOP, is_on); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_stbcal, + MISC_SHU_STBCAL_STBCALEN, is_on); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_stbcal, + MISC_SHU_STBCAL_STB_SELPHCALEN, is_on); + } +} + +static void dramc_reset_delay_chain_before_calibration(void) +{ + u32 bc_bak = dramc_get_broadcast(); + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + + for (u8 rk = RANK_0; rk < RANK_MAX; rk++) { + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + struct ddrphy_ao_regs *phy_ao = &ch[chn].phy_ao; + + SET32_BITFIELDS(&phy_ao->ca_rk[rk].shu_r0_ca_txdly0, + SHU_R0_CA_TXDLY0_TX_ARCA0_DLY, 0, + SHU_R0_CA_TXDLY0_TX_ARCA1_DLY, 0, + SHU_R0_CA_TXDLY0_TX_ARCA2_DLY, 0, + SHU_R0_CA_TXDLY0_TX_ARCA3_DLY, 0); + SET32_BITFIELDS(&phy_ao->ca_rk[rk].shu_r0_ca_txdly1, + SHU_R0_CA_TXDLY1_TX_ARCA4_DLY, 0, + SHU_R0_CA_TXDLY1_TX_ARCA5_DLY, 0, + SHU_R0_CA_TXDLY1_TX_ARCA6_DLY, 0, + SHU_R0_CA_TXDLY1_TX_ARCA7_DLY, 0); + SET32_BITFIELDS(&phy_ao->byte[0].rk[rk].shu_r0_b0_txdly0, + SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0, 0, + SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0, 0, + SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0, 0, + SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0, 0); + SET32_BITFIELDS(&phy_ao->byte[0].rk[rk].shu_r0_b0_txdly1, + SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0, 0, + SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0, 0, + SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0, 0, + SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0, 0); + SET32_BITFIELDS(&phy_ao->byte[1].rk[rk].shu_r0_b0_txdly0, + SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1, 0, + SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1, 0, + SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1, 0, + SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1, 0); + SET32_BITFIELDS(&phy_ao->byte[1].rk[rk].shu_r0_b0_txdly1, + SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1, 0, + SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1, 0, + SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1, 0, + SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1, 0); + SET32_BITFIELDS(&phy_ao->byte[0].rk[rk].shu_r0_b0_txdly3, + SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0, 0x0); + SET32_BITFIELDS(&phy_ao->byte[1].rk[rk].shu_r0_b0_txdly3, + SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1, 0x0); + } + } + + dramc_set_broadcast(bc_bak); +} + +static void dramc_init(const struct ddr_cali *cali) +{ + dramc_reset_delay_chain_before_calibration(); +} + +static void dramc_before_calibration(const struct ddr_cali *cali) +{ + u8 ma_type = get_column_num(); + dram_freq_grp freq_group = cali->freq_group; + u8 dis_imp_hw = (freq_group > DDRFREQ_1200) ? 0 : 1; + + dramc_hw_gating_onoff(false); + + cke_fix_onoff(cali, CHANNEL_A, RANK_MAX, CKE_FIXON); + cke_fix_onoff(cali, CHANNEL_B, RANK_MAX, CKE_FIXON); + + set_cke2rank_independent(); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].ao.shu_tx_set0, SHU_TX_SET0_DBIWR, 0x0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_impedamce_upd_dis1, + MISC_SHU_IMPEDAMCE_UPD_DIS1_ODTN_UPD_DIS, dis_imp_hw, + MISC_SHU_IMPEDAMCE_UPD_DIS1_DRVN_UPD_DIS, dis_imp_hw, + MISC_SHU_IMPEDAMCE_UPD_DIS1_DRVP_UPD_DIS, dis_imp_hw, + MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_ODTN_UPD_DIS, dis_imp_hw, + MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVN_UPD_DIS, dis_imp_hw, + MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVP_UPD_DIS, dis_imp_hw, + MISC_SHU_IMPEDAMCE_UPD_DIS1_DQ_ODTN_UPD_DIS, dis_imp_hw, + MISC_SHU_IMPEDAMCE_UPD_DIS1_DQ_DRVN_UPD_DIS, dis_imp_hw, + MISC_SHU_IMPEDAMCE_UPD_DIS1_DQ_DRVP_UPD_DIS, dis_imp_hw, + MISC_SHU_IMPEDAMCE_UPD_DIS1_DQS_ODTN_UPD_DIS, dis_imp_hw, + MISC_SHU_IMPEDAMCE_UPD_DIS1_DQS_DRVN_UPD_DIS, dis_imp_hw, + MISC_SHU_IMPEDAMCE_UPD_DIS1_DQS_DRVP_UPD_DIS, dis_imp_hw, + MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVP_UPD_DIS, 1, + MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVN_UPD_DIS, 1, + MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_ODTN_UPD_DIS, 1); + + SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_impcal1, + SHU_MISC_IMPCAL1_IMPCALCNT, dis_imp_hw ? 0x0 : 0x40); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_drving1, + SHU_MISC_DRVING1_DIS_IMPCAL_HW, dis_imp_hw); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_drving1, + SHU_MISC_DRVING1_DIS_IMP_ODTN_TRACK, dis_imp_hw); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_drving2, + SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN, dis_imp_hw); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd12, + SHU_CA_CMD12_RG_RIMP_UNTERM_EN, dis_imp_hw); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_clk_ctrl, + MISC_CLK_CTRL_DVFS_CLK_MEM_SEL, 0, + MISC_CLK_CTRL_DVFS_MEM_CK_MUX_UPDATE_EN, 0); + SET32_BITFIELDS(&ch[chn].ao.shu_zq_set0, + SHU_ZQ_SET0_ZQCSCNT, 0x1ff, + SHU_ZQ_SET0_TZQLAT, 0x1b); + SET32_BITFIELDS(&ch[chn].ao.zq_set0, + ZQ_SET0_ZQCSDUAL, 1, + ZQ_SET0_ZQCSMASK_OPT, 0, + ZQ_SET0_ZQMASK_CGAR, 0, + ZQ_SET0_ZQCS_MASK_SEL_CGAR, 0); + } + SET32_BITFIELDS(&ch[0].ao.zq_set0, ZQ_SET0_ZQCSMASK, 1); + SET32_BITFIELDS(&ch[1].ao.zq_set0, ZQ_SET0_ZQCSMASK, 0); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].ao.zq_set0, ZQ_SET0_ZQCS_MASK_SEL, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq2, + SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq2, + SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1, 0); + SET32_BITFIELDS(&ch[chn].ao.dcm_sub_ctrl, + DCM_SUB_CTRL_SUBCLK_CTRL_TX_AUTOK, 0x0); + SET32_BITFIELDS(&ch[chn].ao.dcm_sub_ctrl, + DCM_SUB_CTRL_SUBCLK_CTRL_TX_TRACKING, 0); + SET32_BITFIELDS(&ch[chn].ao.dqsoscr, DQSOSCR_DQSOSCRDIS, 0x1); + SET32_BITFIELDS(&ch[chn].ao.refctrl0, REFCTRL0_REFDIS, 0x1); + SET32_BITFIELDS(&ch[chn].ao.shu_matype, SHU_MATYPE_MATYPE, ma_type); + } + tx_path_algorithm(cali); +} + void dfs_init_for_calibration(const struct ddr_cali *cali) { + dramc_init(cali); + dramc_before_calibration(cali); } diff --git a/src/soc/mediatek/mt8192/emi.c b/src/soc/mediatek/mt8192/emi.c index 893913b..80ee9ed 100644 --- a/src/soc/mediatek/mt8192/emi.c +++ b/src/soc/mediatek/mt8192/emi.c @@ -314,6 +314,17 @@ write32(&ch[chn].emi_chn.cona, emi_con->chn_cona_val); }
+u32 get_column_num(void) +{ + u32 ma_type = read32(&emi_reg->cona); + u32 ma_type_r0 = ((ma_type >> 20) & 0x3) + 1; + u32 ma_type_r1 = ((ma_type >> 22) & 0x3) + 1; + + ma_type = MIN(ma_type_r0, ma_type_r1); + + return ma_type; +} + static void emi_sw_setting(void) { setbits32(&emi_mpu->mpu_ctrl_d[1], BIT(4));
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