Change in coreboot[master]: cpu/amd/pi00730F01: Use common code for mp_init

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64891 )

Change subject: cpu/amd/pi00730F01: Use common code for mp_init
......................................................................

cpu/amd/pi00730F01: Use common code for mp_init

Change-Id: Ia9f0eb3df8fd2dfe395f616da981cc3a0cd3b29d
Signed-off-by: Arthur Heymans 
---
M src/cpu/amd/smm/smm_helper.c
M src/northbridge/amd/pi/00730F01/northbridge.c
2 files changed, 7 insertions(+), 19 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/64891/1

diff --git a/src/cpu/amd/smm/smm_helper.c b/src/cpu/amd/smm/smm_helper.c
index d032db5..515302c 100644
--- a/src/cpu/amd/smm/smm_helper.c
+++ b/src/cpu/amd/smm/smm_helper.c
@@ -128,3 +128,8 @@
    .per_cpu_smm_trigger = smm_relocation_trigger,
    .post_mp_init = global_smi_enable,
 };
+
+const struct mp_ops amd_mp_ops = {
+	.pre_mp_init = pre_mp_init,
+	.get_cpu_count = get_cpu_count,
+};
diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c
index 52364a2..0a53e04 100644
--- a/src/northbridge/amd/pi/00730F01/northbridge.c
+++ b/src/northbridge/amd/pi/00730F01/northbridge.c
@@ -867,28 +867,11 @@
    .acpi_name        = domain_acpi_name,
 };

-static void pre_mp_init(void)
-{
-	x86_setup_mtrrs_with_detect();
-	x86_mtrr_check();
-}
-
-static int get_cpu_count(void)
-{
-	uint8_t siblings = cpuid_ecx(0x80000008) & 0xff;
-
-	return siblings + 1;
-}
-
-static const struct mp_ops mp_ops = {
-	.pre_mp_init = pre_mp_init,
-	.get_cpu_count = get_cpu_count,
-};
-
 void mp_init_cpus(struct bus *cpu_bus)
 {
+	extern const struct mp_ops amd_mp_ops;
    /* TODO: Handle mp_init_with_smm failure? */
-	mp_init_with_smm(cpu_bus, &mp_ops);
+	mp_init_with_smm(cpu_bus, &amd_mp_ops);

/* The flash is now no longer cacheable. Reset to WP for performance. */
    mtrr_use_temp_range(OPTIMAL_CACHE_ROM_BASE, OPTIMAL_CACHE_ROM_SIZE,