Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35732 )
Change subject: intel/fsp_baytrail: Rename from xx_DEV_FUNC ......................................................................
intel/fsp_baytrail: Rename from xx_DEV_FUNC
Change-Id: Id78e594ae6490d39df76317f8fc3381fe681dd6f Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/soc/intel/fsp_baytrail/acpi.c M src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c M src/soc/intel/fsp_baytrail/include/soc/lpc.h M src/soc/intel/fsp_baytrail/include/soc/pci_devs.h 4 files changed, 62 insertions(+), 63 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/35732/1
diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c index fb941ab..59dc6be 100644 --- a/src/soc/intel/fsp_baytrail/acpi.c +++ b/src/soc/intel/fsp_baytrail/acpi.c @@ -175,7 +175,7 @@ void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) { acpi_header_t *header = &(fadt->header); - struct device *lpcdev = pcidev_path_on_root(FADT_SOC_LPC_DEVFN); + struct device *lpcdev = pcidev_path_on_root(PCH_DEVFN_LPC); u16 pmbase = pci_read_config16(lpcdev, ABASE) & 0xfff0; config_t *config = config_of(lpcdev);
diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c index c0b0998..0df07ee 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -79,7 +79,7 @@ DEVTREE_CONST config_t *config; printk(FSP_INFO_LEVEL, "Configure Default UPD Data\n");
- dev = pcidev_path_on_root(SOC_DEV_FUNC); + dev = pcidev_path_on_root(XXX_DEVFN_SOC); config = config_of(dev);
/* Set up default verb tables - Just HDMI audio */ @@ -142,26 +142,26 @@ continue;
switch (dev->path.pci.devfn) { - UPD_DEVICE_CHECK(SDIO_DEV_FUNC, PcdEnableSdio, "Sdio:\t\t\t"); - UPD_DEVICE_CHECK(SD_DEV_FUNC, PcdEnableSdcard, "Sdcard:\t\t\t"); - UPD_DEVICE_CHECK(SIO_DMA1_DEV_FUNC, PcdEnableDma0, "SIO Dma 0:\t\t"); - UPD_DEVICE_CHECK(I2C1_DEV_FUNC, PcdEnableI2C0, "SIO I2C0:\t\t"); - UPD_DEVICE_CHECK(I2C2_DEV_FUNC, PcdEnableI2C1, "SIO I2C1:\t\t"); - UPD_DEVICE_CHECK(I2C3_DEV_FUNC, PcdEnableI2C2, "SIO I2C2:\t\t"); - UPD_DEVICE_CHECK(I2C4_DEV_FUNC, PcdEnableI2C3, "SIO I2C3:\t\t"); - UPD_DEVICE_CHECK(I2C5_DEV_FUNC, PcdEnableI2C4, "SIO I2C4:\t\t"); - UPD_DEVICE_CHECK(I2C6_DEV_FUNC, PcdEnableI2C5, "SIO I2C5:\t\t"); - UPD_DEVICE_CHECK(I2C7_DEV_FUNC, PcdEnableI2C6, "SIO I2C6:\t\t"); - UPD_DEVICE_CHECK(SIO_DMA2_DEV_FUNC, PcdEnableDma1, "SIO Dma1:\t\t"); - UPD_DEVICE_CHECK(PWM1_DEV_FUNC, PcdEnablePwm0, "Pwm0:\t\t\t"); - UPD_DEVICE_CHECK(PWM2_DEV_FUNC, PcdEnablePwm1, "Pwm1:\t\t\t"); - UPD_DEVICE_CHECK(HSUART1_DEV_FUNC, PcdEnableHsuart0, "Hsuart0:\t\t"); - UPD_DEVICE_CHECK(HSUART2_DEV_FUNC, PcdEnableHsuart1, "Hsuart1:\t\t"); - UPD_DEVICE_CHECK(SPI_DEV_FUNC, PcdEnableSpi, "Spi:\t\t\t"); - UPD_DEVICE_CHECK(SATA_DEV_FUNC, PcdEnableSata, "SATA:\t\t\t"); - UPD_DEVICE_CHECK(HDA_DEV_FUNC, PcdEnableAzalia, "Azalia:\t\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_SDIO, PcdEnableSdio, "Sdio:\t\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_SD, PcdEnableSdcard, "Sdcard:\t\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_SIO_DMA1, PcdEnableDma0, "SIO Dma 0:\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_I2C1, PcdEnableI2C0, "SIO I2C0:\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_I2C2, PcdEnableI2C1, "SIO I2C1:\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_I2C3, PcdEnableI2C2, "SIO I2C2:\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_I2C4, PcdEnableI2C3, "SIO I2C3:\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_I2C5, PcdEnableI2C4, "SIO I2C4:\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_I2C6, PcdEnableI2C5, "SIO I2C5:\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_I2C7, PcdEnableI2C6, "SIO I2C6:\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_SIO_DMA2, PcdEnableDma1, "SIO Dma1:\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_PWM1, PcdEnablePwm0, "Pwm0:\t\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_PWM2, PcdEnablePwm1, "Pwm1:\t\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_HSUART1, PcdEnableHsuart0, "Hsuart0:\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_HSUART2, PcdEnableHsuart1, "Hsuart1:\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_SPI, PcdEnableSpi, "Spi:\t\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_SATA, PcdEnableSata, "SATA:\t\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_HDA, PcdEnableAzalia, "Azalia:\t\t\t");
- case MIPI_DEV_FUNC: /* Camera / Image Signal Processing */ + case XXX_DEVFN_MIPI: /* Camera / Image Signal Processing */ if (FspInfo->ImageRevision >= FSP_GOLD3_REV_ID) { UpdData->ISPEnable = dev->enabled; } else { @@ -174,24 +174,24 @@ printk(FSP_INFO_LEVEL, "MIPI/ISP:\t\t%s\n", dev->enabled?"Enabled":"Disabled"); break; - case EMMC_DEV_FUNC: /* EMMC 4.1*/ + case XXX_DEVFN_EMMC: /* EMMC 4.1*/ if ((dev->enabled) && (config->PcdeMMCBootMode == EMMC_FOLLOWS_DEVICETREE)) UpdData->PcdeMMCBootMode = EMMC_4_1 - EMMC_DISABLED; break; - case MMC45_DEV_FUNC: /* MMC 4.5*/ + case XXX_DEVFN_MMC45: /* MMC 4.5*/ if ((dev->enabled) && (config->PcdeMMCBootMode == EMMC_FOLLOWS_DEVICETREE)) UpdData->PcdeMMCBootMode = EMMC_4_5 - EMMC_DISABLED; break; - case XHCI_DEV_FUNC: + case XXX_DEVFN_XHCI: UpdData->PcdEnableXhci = dev->enabled; break; - case EHCI_DEV_FUNC: + case XXX_DEVFN_EHCI: UpdData->PcdEnableXhci = !(dev->enabled); break;
- case LPE_DEV_FUNC: + case XXX_DEVFN_LPE: if (dev->enabled) UpdData->PcdEnableLpe = config->LpeAcpiModeEnable; else diff --git a/src/soc/intel/fsp_baytrail/include/soc/lpc.h b/src/soc/intel/fsp_baytrail/include/soc/lpc.h index 5abe719..defd34a 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/lpc.h +++ b/src/soc/intel/fsp_baytrail/include/soc/lpc.h @@ -17,8 +17,6 @@ #ifndef _BAYTRAIL_LPC_H_ #define _BAYTRAIL_LPC_H_
-#define FADT_SOC_LPC_DEVFN PCI_DEVFN(0x1f, 0) - /* PCI config registers in LPC bridge. */ #define REVID 0x08 #define ABASE 0x40 /* IO BAR */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h b/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h index 5d70879..5f2b1b6 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h +++ b/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h @@ -27,39 +27,39 @@ #define SOC_DEV 0x0 #define SOC_FUNC 0 # define SOC_DEVID 0x0f00 -# define SOC_DEV_FUNC PCI_DEVFN(SOC_DEV,SOC_FUNC) +# define XXX_DEVFN_SOC PCI_DEVFN(SOC_DEV,SOC_FUNC)
/* Graphics and Display */ #define GFX_DEV 0x2 #define GFX_FUNC 0 # define GFX_DEVID 0x0f31 -# define GFX_DEV_FUNC PCI_DEVFN(GFX_DEV,GFX_FUNC) +# define XXX_DEVFN_GFX PCI_DEVFN(GFX_DEV,GFX_FUNC)
/* MIPI */ #define MIPI_DEV 0x3 #define MIPI_FUNC 0 # define MIPI_DEVID 0x0f38 -# define MIPI_DEV_FUNC PCI_DEVFN(MIPI_DEV,MIPI_FUNC) +# define XXX_DEVFN_MIPI PCI_DEVFN(MIPI_DEV,MIPI_FUNC)
/* SDIO Port */ #define EMMC_DEV 0x10 #define EMMC_FUNC 0 # define EMMC_DEVID 0x0f14 -# define EMMC_DEV_FUNC PCI_DEVFN(EMMC_DEV,EMMC_FUNC) +# define XXX_DEVFN_EMMC PCI_DEVFN(EMMC_DEV,EMMC_FUNC)
/* SDIO Port */ #define SDIO_DEV 0x11 #define SDIO_FUNC 0 # define SDIO_DEVID 0x0f15 -# define SDIO_DEV_FUNC PCI_DEVFN(SDIO_DEV,SDIO_FUNC) +# define XXX_DEVFN_SDIO PCI_DEVFN(SDIO_DEV,SDIO_FUNC)
/* SD Port */ #define SD_DEV 0x12 #define SD_FUNC 0 # define SD_DEVID 0x0f16 -# define SD_DEV_FUNC PCI_DEVFN(SD_DEV,SD_FUNC) +# define XXX_DEVFN_SD PCI_DEVFN(SD_DEV,SD_FUNC)
/* SATA */ #define SATA_DEV 0x13 @@ -74,7 +74,7 @@ # define SATA_SP 0xD0 # define SATA_BIST1 0xE4 # define SATA_BIST2 0xE8 -# define SATA_DEV_FUNC PCI_DEVFN(SATA_DEV,SATA_FUNC) +# define XXX_DEVFN_SATA PCI_DEVFN(SATA_DEV,SATA_FUNC)
/* xHCI */ @@ -84,25 +84,25 @@ # define XHCI_FUS_REG 0xE0 # define XHCI_FUNC_DISABLE (1 << 0) # define XHCI_USB2PR_REG 0xD0 -# define XHCI_DEV_FUNC PCI_DEVFN(XHCI_DEV,XHCI_FUNC) +# define XXX_DEVFN_XHCI PCI_DEVFN(XHCI_DEV,XHCI_FUNC)
/* LPE Audio */ #define LPE_DEV 0x15 #define LPE_FUNC 0 # define LPE_DEVID 0x0f28 -# define LPE_DEV_FUNC PCI_DEVFN(LPE_DEV,LPE_FUNC) +# define XXX_DEVFN_LPE PCI_DEVFN(LPE_DEV,LPE_FUNC)
/* OTG */ #define OTG_DEV 0x16 #define OTG_FUNC 0 # define OTG_DEVID 0x0f37 -# define OTG_DEV_FUNC PCI_DEVFN(LPE_DEV,LPE_FUNC) +# define XXX_DEVFN_OTG PCI_DEVFN(LPE_DEV,LPE_FUNC)
/* MMC Port */ #define MMC45_DEV 0x17 #define MMC45_FUNC 0 # define MMC45_DEVID 0x0f50 -# define MMC45_DEV_FUNC PCI_DEVFN(MMC45_DEV,MMC45_FUNC) +# define XXX_DEVFN_MMC45 PCI_DEVFN(MMC45_DEV,MMC45_FUNC)
/* Serial IO 1 */ #define SIO1_DEV 0x18 @@ -130,26 +130,26 @@ # define I2C7_DEV SIO1_DEV # define I2C7_FUNC 7 # define I2C7_DEVID 0x0f47 -# define SIO_DMA1_DEV_FUNC PCI_DEVFN(SIO_DMA1_DEV,SIO_DMA1_FUNC) -# define I2C1_DEV_FUNC PCI_DEVFN(I2C1_DEV,I2C1_FUNC) -# define I2C2_DEV_FUNC PCI_DEVFN(I2C2_DEV,I2C2_FUNC) -# define I2C3_DEV_FUNC PCI_DEVFN(I2C3_DEV,I2C3_FUNC) -# define I2C4_DEV_FUNC PCI_DEVFN(I2C4_DEV,I2C4_FUNC) -# define I2C5_DEV_FUNC PCI_DEVFN(I2C5_DEV,I2C5_FUNC) -# define I2C6_DEV_FUNC PCI_DEVFN(I2C6_DEV,I2C6_FUNC) -# define I2C7_DEV_FUNC PCI_DEVFN(I2C7_DEV,I2C7_FUNC) +# define XXX_DEVFN_SIO_DMA1 PCI_DEVFN(SIO_DMA1_DEV,SIO_DMA1_FUNC) +# define XXX_DEVFN_I2C1 PCI_DEVFN(I2C1_DEV,I2C1_FUNC) +# define XXX_DEVFN_I2C2 PCI_DEVFN(I2C2_DEV,I2C2_FUNC) +# define XXX_DEVFN_I2C3 PCI_DEVFN(I2C3_DEV,I2C3_FUNC) +# define XXX_DEVFN_I2C4 PCI_DEVFN(I2C4_DEV,I2C4_FUNC) +# define XXX_DEVFN_I2C5 PCI_DEVFN(I2C5_DEV,I2C5_FUNC) +# define XXX_DEVFN_I2C6 PCI_DEVFN(I2C6_DEV,I2C6_FUNC) +# define XXX_DEVFN_I2C7 PCI_DEVFN(I2C7_DEV,I2C7_FUNC)
/* Trusted Execution Engine */ #define TXE_DEV 0x1a #define TXE_FUNC 0 # define TXE_DEVID 0x0f18 -# define TXE_DEV_FUNC PCI_DEVFN(TXE_DEV,TXE_FUNC) +# define XXX_DEVFN_TXE PCI_DEVFN(TXE_DEV,TXE_FUNC)
/* HD Audio */ #define HDA_DEV 0x1b #define HDA_FUNC 0 # define HDA_DEVID 0x0f04 -# define HDA_DEV_FUNC PCI_DEVFN(HDA_DEV,HDA_FUNC) +# define XXX_DEVFN_HDA PCI_DEVFN(HDA_DEV,HDA_FUNC) # define HDA_AZUBAR 0x14 # define HDA_MMLA 0x64 # define HDA_MMUA 0x68 @@ -168,16 +168,16 @@ # define PCIE_PORT4_DEV PCIE_DEV # define PCIE_PORT4_FUNC 3 # define PCIE_PORT4_DEVID 0x0f4e -# define PCIE_PORT1_DEV_FUNC PCI_DEVFN(PCIE_DEV,PCIE_PORT1_FUNC) -# define PCIE_PORT2_DEV_FUNC PCI_DEVFN(PCIE_DEV,PCIE_PORT2_FUNC) -# define PCIE_PORT3_DEV_FUNC PCI_DEVFN(PCIE_DEV,PCIE_PORT3_FUNC) -# define PCIE_PORT4_DEV_FUNC PCI_DEVFN(PCIE_DEV,PCIE_PORT4_FUNC) +# define XXX_DEVFN_PCIE_PORT1 PCI_DEVFN(PCIE_DEV,PCIE_PORT1_FUNC) +# define XXX_DEVFN_PCIE_PORT2 PCI_DEVFN(PCIE_DEV,PCIE_PORT2_FUNC) +# define XXX_DEVFN_PCIE_PORT3 PCI_DEVFN(PCIE_DEV,PCIE_PORT3_FUNC) +# define XXX_DEVFN_PCIE_PORT4 PCI_DEVFN(PCIE_DEV,PCIE_PORT4_FUNC)
/* EHCI */ #define EHCI_DEV 0x1d #define EHCI_FUNC 0 # define EHCI_DEVID 0x0f34 -# define EHCI_DEV_FUNC PCI_DEVFN(EHCI_DEV,EHCI_FUNC) +# define XXX_DEVFN_EHCI PCI_DEVFN(EHCI_DEV,EHCI_FUNC)
/* Serial IO 2 */ #define SIO2_DEV 0x1e @@ -199,12 +199,12 @@ # define SPI_DEV SIO2_DEV # define SPI_FUNC 5 # define SPI_DEVID 0xf0e -# define SIO_DMA2_DEV_FUNC PCI_DEVFN(SIO_DMA2_DEV,SIO_DMA2_FUNC) -# define PWM1_DEV_FUNC PCI_DEVFN(PWM1_DEV,PWM1_FUNC) -# define PWM2_DEV_FUNC PCI_DEVFN(PWM2_DEV,PWM2_FUNC) -# define HSUART1_DEV_FUNC PCI_DEVFN(HSUART1_DEV,HSUART1_FUNC) -# define HSUART2_DEV_FUNC PCI_DEVFN(HSUART2_DEV,HSUART2_FUNC) -# define SPI_DEV_FUNC PCI_DEVFN(SPI_DEV,SPI_FUNC) +# define XXX_DEVFN_SIO_DMA2 PCI_DEVFN(SIO_DMA2_DEV,SIO_DMA2_FUNC) +# define XXX_DEVFN_PWM1 PCI_DEVFN(PWM1_DEV,PWM1_FUNC) +# define XXX_DEVFN_PWM2 PCI_DEVFN(PWM2_DEV,PWM2_FUNC) +# define XXX_DEVFN_HSUART1 PCI_DEVFN(HSUART1_DEV,HSUART1_FUNC) +# define XXX_DEVFN_HSUART2 PCI_DEVFN(HSUART2_DEV,HSUART2_FUNC) +# define XXX_DEVFN_SPI PCI_DEVFN(SPI_DEV,SPI_FUNC)
/* Platform Controller Unit */ @@ -212,11 +212,12 @@ # define LPC_DEV PCU_DEV # define LPC_FUNC 0 # define LPC_DEVID 0x0f1c +# define PCH_DEVFN_LPC PCI_DEVFN(LPC_DEV,LPC_FUNC) +# define LPC_BDF PCI_DEV(0, LPC_DEV, LPC_FUNC) + # define SMBUS_DEV PCU_DEV # define SMBUS_FUNC 3 # define SMBUS_DEVID 0x0f12 -# define LPC_DEV_FUNC PCI_DEVFN(LPC_DEV,LPC_FUNC) -# define LPC_BDF PCI_DEV(0, LPC_DEV, LPC_FUNC) -# define SMBUS_DEV_FUNC PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC) +# define XXX_DEVFN_SMBUS PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC)
#endif /* _BAYTRAIL_PCI_DEVS_H_ */
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35732 )
Change subject: intel/fsp_baytrail: Rename from xx_DEV_FUNC ......................................................................
Patch Set 1:
Conventions and consistency with naming helps. We are currently evaluating ways to replace some/most/lot of pci_devfn_t with struct device *, and potentially auto-generating these _DEVFN_ from devicetree.cb where necessary.
The prefix XXX_ is arbitrary. Would SCH_ or PCH_ be somewhat correct?
Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35732 )
Change subject: intel/fsp_baytrail: Rename from xx_DEV_FUNC ......................................................................
Patch Set 1:
With this change, do you had in mind to find out how much of these devices are rally used adn let Jenkins do the job? You will for sure abandon it once you get the info, right?
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35732 )
Change subject: intel/fsp_baytrail: Rename from xx_DEV_FUNC ......................................................................
Patch Set 1:
Patch Set 1:
With this change, do you had in mind to find out how much of these devices are rally used adn let Jenkins do the job? You will for sure abandon it once you get the info, right?
Why would it break on jenkins when I renamed all occasions?
Intel adopted xx_DEVFN_xx naming for macros expanding to PCI_DEVFN() starting with apollolake, why should we have older soc/ use different naming scheme?
Hello Werner Zeh, Aaron Durbin, Patrick Rudolph, Huang Jin, Arthur Heymans, Philipp Deppenwiese, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35732
to look at the new patch set (#2).
Change subject: intel/fsp_baytrail: Rename from xx_DEV_FUNC ......................................................................
intel/fsp_baytrail: Rename from xx_DEV_FUNC
Intel adopted xx_DEVFN_xx naming for macros expanding to PCI_DEVFN() starting with apollolake. The ones named xx_DEV_FUNC are being renamed, or dropped, if they were generally not used at all for a platform.
Change-Id: Id78e594ae6490d39df76317f8fc3381fe681dd6f Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/soc/intel/fsp_baytrail/acpi.c M src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c M src/soc/intel/fsp_baytrail/include/soc/lpc.h M src/soc/intel/fsp_baytrail/include/soc/pci_devs.h 4 files changed, 62 insertions(+), 64 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/35732/2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35732 )
Change subject: intel/fsp_baytrail: Rename from xx_DEV_FUNC ......................................................................
Patch Set 3:
(37 comments)
https://review.coreboot.org/c/coreboot/+/35732/3/src/soc/intel/fsp_baytrail/... File src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c:
https://review.coreboot.org/c/coreboot/+/35732/3/src/soc/intel/fsp_baytrail/... PS3, Line 144: switch (dev->path.pci.devfn) { switch and case should be at the same indent
https://review.coreboot.org/c/coreboot/+/35732/3/src/soc/intel/fsp_baytrail/... PS3, Line 164: case XXX_DEVFN_MIPI: /* Camera / Image Signal Processing */ Possible switch case/default not preceded by break or fallthrough comment
https://review.coreboot.org/c/coreboot/+/35732/3/src/soc/intel/fsp_baytrail/... File src/soc/intel/fsp_baytrail/include/soc/pci_devs.h:
https://review.coreboot.org/c/coreboot/+/35732/3/src/soc/intel/fsp_baytrail/... PS3, Line 29: # define XXX_DEVFN_SOC PCI_DEVFN(SOC_DEV,SOC_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/3/src/soc/intel/fsp_baytrail/... PS3, Line 35: # define XXX_DEVFN_GFX PCI_DEVFN(GFX_DEV,GFX_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/3/src/soc/intel/fsp_baytrail/... PS3, Line 40: # define XXX_DEVFN_MIPI PCI_DEVFN(MIPI_DEV,MIPI_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/3/src/soc/intel/fsp_baytrail/... PS3, Line 46: # define XXX_DEVFN_EMMC PCI_DEVFN(EMMC_DEV,EMMC_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/3/src/soc/intel/fsp_baytrail/... PS3, Line 51: # define XXX_DEVFN_SDIO PCI_DEVFN(SDIO_DEV,SDIO_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/3/src/soc/intel/fsp_baytrail/... PS3, Line 56: # define XXX_DEVFN_SD PCI_DEVFN(SD_DEV,SD_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/3/src/soc/intel/fsp_baytrail/... PS3, Line 61: # define XXX_DEVFN_SATA PCI_DEVFN(SATA_DEV,SATA_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/3/src/soc/intel/fsp_baytrail/... PS3, Line 69: # define XXX_DEVFN_XHCI PCI_DEVFN(XHCI_DEV,XHCI_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/3/src/soc/intel/fsp_baytrail/... PS3, Line 74: # define XXX_DEVFN_LPE PCI_DEVFN(LPE_DEV,LPE_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/3/src/soc/intel/fsp_baytrail/... PS3, Line 79: # define XXX_DEVFN_OTG PCI_DEVFN(LPE_DEV,LPE_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/3/src/soc/intel/fsp_baytrail/... PS3, Line 84: # define XXX_DEVFN_MMC45 PCI_DEVFN(MMC45_DEV,MMC45_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/3/src/soc/intel/fsp_baytrail/... PS3, Line 104: # define XXX_DEVFN_SIO_DMA1 PCI_DEVFN(SIO_DMA1_DEV,SIO_DMA1_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/3/src/soc/intel/fsp_baytrail/... PS3, Line 105: # define XXX_DEVFN_I2C1 PCI_DEVFN(I2C1_DEV,I2C1_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/3/src/soc/intel/fsp_baytrail/... PS3, Line 106: # define XXX_DEVFN_I2C2 PCI_DEVFN(I2C2_DEV,I2C2_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/3/src/soc/intel/fsp_baytrail/... PS3, Line 107: # define XXX_DEVFN_I2C3 PCI_DEVFN(I2C3_DEV,I2C3_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/3/src/soc/intel/fsp_baytrail/... PS3, Line 108: # define XXX_DEVFN_I2C4 PCI_DEVFN(I2C4_DEV,I2C4_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/3/src/soc/intel/fsp_baytrail/... PS3, Line 109: # define XXX_DEVFN_I2C5 PCI_DEVFN(I2C5_DEV,I2C5_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/3/src/soc/intel/fsp_baytrail/... PS3, Line 110: # define XXX_DEVFN_I2C6 PCI_DEVFN(I2C6_DEV,I2C6_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/3/src/soc/intel/fsp_baytrail/... PS3, Line 111: # define XXX_DEVFN_I2C7 PCI_DEVFN(I2C7_DEV,I2C7_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/3/src/soc/intel/fsp_baytrail/... PS3, Line 116: # define XXX_DEVFN_TXE PCI_DEVFN(TXE_DEV,TXE_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/3/src/soc/intel/fsp_baytrail/... PS3, Line 121: # define XXX_DEVFN_HDA PCI_DEVFN(HDA_DEV,HDA_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/3/src/soc/intel/fsp_baytrail/... PS3, Line 133: # define XXX_DEVFN_PCIE_PORT1 PCI_DEVFN(PCIE_DEV,PCIE_PORT1_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/3/src/soc/intel/fsp_baytrail/... PS3, Line 134: # define XXX_DEVFN_PCIE_PORT2 PCI_DEVFN(PCIE_DEV,PCIE_PORT2_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/3/src/soc/intel/fsp_baytrail/... PS3, Line 135: # define XXX_DEVFN_PCIE_PORT3 PCI_DEVFN(PCIE_DEV,PCIE_PORT3_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/3/src/soc/intel/fsp_baytrail/... PS3, Line 136: # define XXX_DEVFN_PCIE_PORT4 PCI_DEVFN(PCIE_DEV,PCIE_PORT4_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/3/src/soc/intel/fsp_baytrail/... PS3, Line 141: # define XXX_DEVFN_EHCI PCI_DEVFN(EHCI_DEV,EHCI_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/3/src/soc/intel/fsp_baytrail/... PS3, Line 157: # define XXX_DEVFN_SIO_DMA2 PCI_DEVFN(SIO_DMA2_DEV,SIO_DMA2_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/3/src/soc/intel/fsp_baytrail/... PS3, Line 158: # define XXX_DEVFN_PWM1 PCI_DEVFN(PWM1_DEV,PWM1_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/3/src/soc/intel/fsp_baytrail/... PS3, Line 159: # define XXX_DEVFN_PWM2 PCI_DEVFN(PWM2_DEV,PWM2_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/3/src/soc/intel/fsp_baytrail/... PS3, Line 160: # define XXX_DEVFN_HSUART1 PCI_DEVFN(HSUART1_DEV,HSUART1_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/3/src/soc/intel/fsp_baytrail/... PS3, Line 161: # define XXX_DEVFN_HSUART2 PCI_DEVFN(HSUART2_DEV,HSUART2_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/3/src/soc/intel/fsp_baytrail/... PS3, Line 162: # define XXX_DEVFN_SPI PCI_DEVFN(SPI_DEV,SPI_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/3/src/soc/intel/fsp_baytrail/... PS3, Line 169: # define PCH_DEVFN_LPC PCI_DEVFN(LPC_DEV,LPC_FUNC) please, no space before tabs
https://review.coreboot.org/c/coreboot/+/35732/3/src/soc/intel/fsp_baytrail/... PS3, Line 169: # define PCH_DEVFN_LPC PCI_DEVFN(LPC_DEV,LPC_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/3/src/soc/intel/fsp_baytrail/... PS3, Line 174: # define XXX_DEVFN_SMBUS PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC) space required after that ',' (ctx:VxV)
Hello Werner Zeh, Aaron Durbin, Patrick Rudolph, Huang Jin, Arthur Heymans, Philipp Deppenwiese, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35732
to look at the new patch set (#4).
Change subject: intel/fsp_baytrail: Rename from xx_DEV_FUNC ......................................................................
intel/fsp_baytrail: Rename from xx_DEV_FUNC
Intel adopted xx_DEVFN_xx naming for macros expanding to PCI_DEVFN() starting with apollolake. The ones named xx_DEV_FUNC are being renamed, or dropped, if they were generally not used at all for a platform.
Change-Id: Id78e594ae6490d39df76317f8fc3381fe681dd6f Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/soc/intel/fsp_baytrail/acpi.c M src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c M src/soc/intel/fsp_baytrail/include/soc/lpc.h M src/soc/intel/fsp_baytrail/include/soc/pci_devs.h 4 files changed, 62 insertions(+), 64 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/35732/4
Hello Werner Zeh, Aaron Durbin, Patrick Rudolph, Huang Jin, Arthur Heymans, Philipp Deppenwiese, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35732
to look at the new patch set (#5).
Change subject: intel/fsp_baytrail: Rename from xx_DEV_FUNC ......................................................................
intel/fsp_baytrail: Rename from xx_DEV_FUNC
Intel adopted xx_DEVFN_xx naming for macros expanding to PCI_DEVFN() starting with apollolake. The ones named xx_DEV_FUNC are being renamed, or dropped, if they were generally not used at all for a platform.
Change-Id: Id78e594ae6490d39df76317f8fc3381fe681dd6f Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/soc/intel/fsp_baytrail/acpi.c M src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c M src/soc/intel/fsp_baytrail/include/soc/lpc.h M src/soc/intel/fsp_baytrail/include/soc/pci_devs.h 4 files changed, 62 insertions(+), 64 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/35732/5
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35732 )
Change subject: intel/fsp_baytrail: Rename from xx_DEV_FUNC ......................................................................
Patch Set 5:
(37 comments)
https://review.coreboot.org/c/coreboot/+/35732/5/src/soc/intel/fsp_baytrail/... File src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c:
https://review.coreboot.org/c/coreboot/+/35732/5/src/soc/intel/fsp_baytrail/... PS5, Line 144: switch (dev->path.pci.devfn) { switch and case should be at the same indent
https://review.coreboot.org/c/coreboot/+/35732/5/src/soc/intel/fsp_baytrail/... PS5, Line 164: case SOC_DEVFN_MIPI: /* Camera / Image Signal Processing */ Possible switch case/default not preceded by break or fallthrough comment
https://review.coreboot.org/c/coreboot/+/35732/5/src/soc/intel/fsp_baytrail/... File src/soc/intel/fsp_baytrail/include/soc/pci_devs.h:
https://review.coreboot.org/c/coreboot/+/35732/5/src/soc/intel/fsp_baytrail/... PS5, Line 29: # define SOC_DEVFN_SOC PCI_DEVFN(SOC_DEV,SOC_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/5/src/soc/intel/fsp_baytrail/... PS5, Line 35: # define SOC_DEVFN_GFX PCI_DEVFN(GFX_DEV,GFX_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/5/src/soc/intel/fsp_baytrail/... PS5, Line 40: # define SOC_DEVFN_MIPI PCI_DEVFN(MIPI_DEV,MIPI_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/5/src/soc/intel/fsp_baytrail/... PS5, Line 46: # define SOC_DEVFN_EMMC PCI_DEVFN(EMMC_DEV,EMMC_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/5/src/soc/intel/fsp_baytrail/... PS5, Line 51: # define SOC_DEVFN_SDIO PCI_DEVFN(SDIO_DEV,SDIO_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/5/src/soc/intel/fsp_baytrail/... PS5, Line 56: # define SOC_DEVFN_SD PCI_DEVFN(SD_DEV,SD_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/5/src/soc/intel/fsp_baytrail/... PS5, Line 61: # define SOC_DEVFN_SATA PCI_DEVFN(SATA_DEV,SATA_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/5/src/soc/intel/fsp_baytrail/... PS5, Line 69: # define SOC_DEVFN_XHCI PCI_DEVFN(XHCI_DEV,XHCI_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/5/src/soc/intel/fsp_baytrail/... PS5, Line 74: # define SOC_DEVFN_LPE PCI_DEVFN(LPE_DEV,LPE_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/5/src/soc/intel/fsp_baytrail/... PS5, Line 79: # define SOC_DEVFN_OTG PCI_DEVFN(LPE_DEV,LPE_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/5/src/soc/intel/fsp_baytrail/... PS5, Line 84: # define SOC_DEVFN_MMC45 PCI_DEVFN(MMC45_DEV,MMC45_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/5/src/soc/intel/fsp_baytrail/... PS5, Line 104: # define SOC_DEVFN_SIO_DMA1 PCI_DEVFN(SIO_DMA1_DEV,SIO_DMA1_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/5/src/soc/intel/fsp_baytrail/... PS5, Line 105: # define SOC_DEVFN_I2C1 PCI_DEVFN(I2C1_DEV,I2C1_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/5/src/soc/intel/fsp_baytrail/... PS5, Line 106: # define SOC_DEVFN_I2C2 PCI_DEVFN(I2C2_DEV,I2C2_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/5/src/soc/intel/fsp_baytrail/... PS5, Line 107: # define SOC_DEVFN_I2C3 PCI_DEVFN(I2C3_DEV,I2C3_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/5/src/soc/intel/fsp_baytrail/... PS5, Line 108: # define SOC_DEVFN_I2C4 PCI_DEVFN(I2C4_DEV,I2C4_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/5/src/soc/intel/fsp_baytrail/... PS5, Line 109: # define SOC_DEVFN_I2C5 PCI_DEVFN(I2C5_DEV,I2C5_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/5/src/soc/intel/fsp_baytrail/... PS5, Line 110: # define SOC_DEVFN_I2C6 PCI_DEVFN(I2C6_DEV,I2C6_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/5/src/soc/intel/fsp_baytrail/... PS5, Line 111: # define SOC_DEVFN_I2C7 PCI_DEVFN(I2C7_DEV,I2C7_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/5/src/soc/intel/fsp_baytrail/... PS5, Line 116: # define SOC_DEVFN_TXE PCI_DEVFN(TXE_DEV,TXE_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/5/src/soc/intel/fsp_baytrail/... PS5, Line 121: # define SOC_DEVFN_HDA PCI_DEVFN(HDA_DEV,HDA_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/5/src/soc/intel/fsp_baytrail/... PS5, Line 133: # define SOC_DEVFN_PCIE_PORT1 PCI_DEVFN(PCIE_DEV,PCIE_PORT1_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/5/src/soc/intel/fsp_baytrail/... PS5, Line 134: # define SOC_DEVFN_PCIE_PORT2 PCI_DEVFN(PCIE_DEV,PCIE_PORT2_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/5/src/soc/intel/fsp_baytrail/... PS5, Line 135: # define SOC_DEVFN_PCIE_PORT3 PCI_DEVFN(PCIE_DEV,PCIE_PORT3_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/5/src/soc/intel/fsp_baytrail/... PS5, Line 136: # define SOC_DEVFN_PCIE_PORT4 PCI_DEVFN(PCIE_DEV,PCIE_PORT4_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/5/src/soc/intel/fsp_baytrail/... PS5, Line 141: # define SOC_DEVFN_EHCI PCI_DEVFN(EHCI_DEV,EHCI_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/5/src/soc/intel/fsp_baytrail/... PS5, Line 157: # define SOC_DEVFN_SIO_DMA2 PCI_DEVFN(SIO_DMA2_DEV,SIO_DMA2_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/5/src/soc/intel/fsp_baytrail/... PS5, Line 158: # define SOC_DEVFN_PWM1 PCI_DEVFN(PWM1_DEV,PWM1_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/5/src/soc/intel/fsp_baytrail/... PS5, Line 159: # define SOC_DEVFN_PWM2 PCI_DEVFN(PWM2_DEV,PWM2_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/5/src/soc/intel/fsp_baytrail/... PS5, Line 160: # define SOC_DEVFN_HSUART1 PCI_DEVFN(HSUART1_DEV,HSUART1_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/5/src/soc/intel/fsp_baytrail/... PS5, Line 161: # define SOC_DEVFN_HSUART2 PCI_DEVFN(HSUART2_DEV,HSUART2_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/5/src/soc/intel/fsp_baytrail/... PS5, Line 162: # define SOC_DEVFN_SPI PCI_DEVFN(SPI_DEV,SPI_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/5/src/soc/intel/fsp_baytrail/... PS5, Line 169: # define PCH_DEVFN_LPC PCI_DEVFN(LPC_DEV,LPC_FUNC) please, no space before tabs
https://review.coreboot.org/c/coreboot/+/35732/5/src/soc/intel/fsp_baytrail/... PS5, Line 169: # define PCH_DEVFN_LPC PCI_DEVFN(LPC_DEV,LPC_FUNC) space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/35732/5/src/soc/intel/fsp_baytrail/... PS5, Line 174: # define SOC_DEVFN_SMBUS PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC) space required after that ',' (ctx:VxV)
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35732 )
Change subject: intel/fsp_baytrail: Rename from xx_DEV_FUNC ......................................................................
Patch Set 5: Code-Review+2
Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35732 )
Change subject: intel/fsp_baytrail: Rename from xx_DEV_FUNC ......................................................................
intel/fsp_baytrail: Rename from xx_DEV_FUNC
Intel adopted xx_DEVFN_xx naming for macros expanding to PCI_DEVFN() starting with apollolake. The ones named xx_DEV_FUNC are being renamed, or dropped, if they were generally not used at all for a platform.
Change-Id: Id78e594ae6490d39df76317f8fc3381fe681dd6f Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/35732 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Aaron Durbin adurbin@chromium.org --- M src/soc/intel/fsp_baytrail/acpi.c M src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c M src/soc/intel/fsp_baytrail/include/soc/lpc.h M src/soc/intel/fsp_baytrail/include/soc/pci_devs.h 4 files changed, 62 insertions(+), 64 deletions(-)
Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved
diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c index fb941ab..59dc6be 100644 --- a/src/soc/intel/fsp_baytrail/acpi.c +++ b/src/soc/intel/fsp_baytrail/acpi.c @@ -175,7 +175,7 @@ void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) { acpi_header_t *header = &(fadt->header); - struct device *lpcdev = pcidev_path_on_root(FADT_SOC_LPC_DEVFN); + struct device *lpcdev = pcidev_path_on_root(PCH_DEVFN_LPC); u16 pmbase = pci_read_config16(lpcdev, ABASE) & 0xfff0; config_t *config = config_of(lpcdev);
diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c index c0b0998..01c876d 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -79,7 +79,7 @@ DEVTREE_CONST config_t *config; printk(FSP_INFO_LEVEL, "Configure Default UPD Data\n");
- dev = pcidev_path_on_root(SOC_DEV_FUNC); + dev = pcidev_path_on_root(SOC_DEVFN_SOC); config = config_of(dev);
/* Set up default verb tables - Just HDMI audio */ @@ -142,26 +142,26 @@ continue;
switch (dev->path.pci.devfn) { - UPD_DEVICE_CHECK(SDIO_DEV_FUNC, PcdEnableSdio, "Sdio:\t\t\t"); - UPD_DEVICE_CHECK(SD_DEV_FUNC, PcdEnableSdcard, "Sdcard:\t\t\t"); - UPD_DEVICE_CHECK(SIO_DMA1_DEV_FUNC, PcdEnableDma0, "SIO Dma 0:\t\t"); - UPD_DEVICE_CHECK(I2C1_DEV_FUNC, PcdEnableI2C0, "SIO I2C0:\t\t"); - UPD_DEVICE_CHECK(I2C2_DEV_FUNC, PcdEnableI2C1, "SIO I2C1:\t\t"); - UPD_DEVICE_CHECK(I2C3_DEV_FUNC, PcdEnableI2C2, "SIO I2C2:\t\t"); - UPD_DEVICE_CHECK(I2C4_DEV_FUNC, PcdEnableI2C3, "SIO I2C3:\t\t"); - UPD_DEVICE_CHECK(I2C5_DEV_FUNC, PcdEnableI2C4, "SIO I2C4:\t\t"); - UPD_DEVICE_CHECK(I2C6_DEV_FUNC, PcdEnableI2C5, "SIO I2C5:\t\t"); - UPD_DEVICE_CHECK(I2C7_DEV_FUNC, PcdEnableI2C6, "SIO I2C6:\t\t"); - UPD_DEVICE_CHECK(SIO_DMA2_DEV_FUNC, PcdEnableDma1, "SIO Dma1:\t\t"); - UPD_DEVICE_CHECK(PWM1_DEV_FUNC, PcdEnablePwm0, "Pwm0:\t\t\t"); - UPD_DEVICE_CHECK(PWM2_DEV_FUNC, PcdEnablePwm1, "Pwm1:\t\t\t"); - UPD_DEVICE_CHECK(HSUART1_DEV_FUNC, PcdEnableHsuart0, "Hsuart0:\t\t"); - UPD_DEVICE_CHECK(HSUART2_DEV_FUNC, PcdEnableHsuart1, "Hsuart1:\t\t"); - UPD_DEVICE_CHECK(SPI_DEV_FUNC, PcdEnableSpi, "Spi:\t\t\t"); - UPD_DEVICE_CHECK(SATA_DEV_FUNC, PcdEnableSata, "SATA:\t\t\t"); - UPD_DEVICE_CHECK(HDA_DEV_FUNC, PcdEnableAzalia, "Azalia:\t\t\t"); + UPD_DEVICE_CHECK(SOC_DEVFN_SDIO, PcdEnableSdio, "Sdio:\t\t\t"); + UPD_DEVICE_CHECK(SOC_DEVFN_SD, PcdEnableSdcard, "Sdcard:\t\t\t"); + UPD_DEVICE_CHECK(SOC_DEVFN_SIO_DMA1, PcdEnableDma0, "SIO Dma 0:\t\t"); + UPD_DEVICE_CHECK(SOC_DEVFN_I2C1, PcdEnableI2C0, "SIO I2C0:\t\t"); + UPD_DEVICE_CHECK(SOC_DEVFN_I2C2, PcdEnableI2C1, "SIO I2C1:\t\t"); + UPD_DEVICE_CHECK(SOC_DEVFN_I2C3, PcdEnableI2C2, "SIO I2C2:\t\t"); + UPD_DEVICE_CHECK(SOC_DEVFN_I2C4, PcdEnableI2C3, "SIO I2C3:\t\t"); + UPD_DEVICE_CHECK(SOC_DEVFN_I2C5, PcdEnableI2C4, "SIO I2C4:\t\t"); + UPD_DEVICE_CHECK(SOC_DEVFN_I2C6, PcdEnableI2C5, "SIO I2C5:\t\t"); + UPD_DEVICE_CHECK(SOC_DEVFN_I2C7, PcdEnableI2C6, "SIO I2C6:\t\t"); + UPD_DEVICE_CHECK(SOC_DEVFN_SIO_DMA2, PcdEnableDma1, "SIO Dma1:\t\t"); + UPD_DEVICE_CHECK(SOC_DEVFN_PWM1, PcdEnablePwm0, "Pwm0:\t\t\t"); + UPD_DEVICE_CHECK(SOC_DEVFN_PWM2, PcdEnablePwm1, "Pwm1:\t\t\t"); + UPD_DEVICE_CHECK(SOC_DEVFN_HSUART1, PcdEnableHsuart0, "Hsuart0:\t\t"); + UPD_DEVICE_CHECK(SOC_DEVFN_HSUART2, PcdEnableHsuart1, "Hsuart1:\t\t"); + UPD_DEVICE_CHECK(SOC_DEVFN_SPI, PcdEnableSpi, "Spi:\t\t\t"); + UPD_DEVICE_CHECK(SOC_DEVFN_SATA, PcdEnableSata, "SATA:\t\t\t"); + UPD_DEVICE_CHECK(SOC_DEVFN_HDA, PcdEnableAzalia, "Azalia:\t\t\t");
- case MIPI_DEV_FUNC: /* Camera / Image Signal Processing */ + case SOC_DEVFN_MIPI: /* Camera / Image Signal Processing */ if (FspInfo->ImageRevision >= FSP_GOLD3_REV_ID) { UpdData->ISPEnable = dev->enabled; } else { @@ -174,24 +174,24 @@ printk(FSP_INFO_LEVEL, "MIPI/ISP:\t\t%s\n", dev->enabled?"Enabled":"Disabled"); break; - case EMMC_DEV_FUNC: /* EMMC 4.1*/ + case SOC_DEVFN_EMMC: /* EMMC 4.1*/ if ((dev->enabled) && (config->PcdeMMCBootMode == EMMC_FOLLOWS_DEVICETREE)) UpdData->PcdeMMCBootMode = EMMC_4_1 - EMMC_DISABLED; break; - case MMC45_DEV_FUNC: /* MMC 4.5*/ + case SOC_DEVFN_MMC45: /* MMC 4.5*/ if ((dev->enabled) && (config->PcdeMMCBootMode == EMMC_FOLLOWS_DEVICETREE)) UpdData->PcdeMMCBootMode = EMMC_4_5 - EMMC_DISABLED; break; - case XHCI_DEV_FUNC: + case SOC_DEVFN_XHCI: UpdData->PcdEnableXhci = dev->enabled; break; - case EHCI_DEV_FUNC: + case SOC_DEVFN_EHCI: UpdData->PcdEnableXhci = !(dev->enabled); break;
- case LPE_DEV_FUNC: + case SOC_DEVFN_LPE: if (dev->enabled) UpdData->PcdEnableLpe = config->LpeAcpiModeEnable; else diff --git a/src/soc/intel/fsp_baytrail/include/soc/lpc.h b/src/soc/intel/fsp_baytrail/include/soc/lpc.h index 5abe719..defd34a 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/lpc.h +++ b/src/soc/intel/fsp_baytrail/include/soc/lpc.h @@ -17,8 +17,6 @@ #ifndef _BAYTRAIL_LPC_H_ #define _BAYTRAIL_LPC_H_
-#define FADT_SOC_LPC_DEVFN PCI_DEVFN(0x1f, 0) - /* PCI config registers in LPC bridge. */ #define REVID 0x08 #define ABASE 0x40 /* IO BAR */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h b/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h index a920194..00ff268 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h +++ b/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h @@ -26,40 +26,39 @@ /* SoC transaction router */ #define SOC_DEV 0x0 #define SOC_FUNC 0 -# define SOC_DEV_FUNC PCI_DEVFN(SOC_DEV,SOC_FUNC) +# define SOC_DEVFN_SOC PCI_DEVFN(SOC_DEV,SOC_FUNC)
/* Graphics and Display */ #define GFX_DEV 0x2 #define GFX_FUNC 0 -# define GFX_DEV_FUNC PCI_DEVFN(GFX_DEV,GFX_FUNC) +# define SOC_DEVFN_GFX PCI_DEVFN(GFX_DEV,GFX_FUNC)
/* MIPI */ #define MIPI_DEV 0x3 #define MIPI_FUNC 0 -# define MIPI_DEV_FUNC PCI_DEVFN(MIPI_DEV,MIPI_FUNC) +# define SOC_DEVFN_MIPI PCI_DEVFN(MIPI_DEV,MIPI_FUNC)
/* SDIO Port */ #define EMMC_DEV 0x10 #define EMMC_FUNC 0 -# define EMMC_DEV_FUNC PCI_DEVFN(EMMC_DEV,EMMC_FUNC) +# define SOC_DEVFN_EMMC PCI_DEVFN(EMMC_DEV,EMMC_FUNC)
/* SDIO Port */ #define SDIO_DEV 0x11 #define SDIO_FUNC 0 -# define SDIO_DEV_FUNC PCI_DEVFN(SDIO_DEV,SDIO_FUNC) +# define SOC_DEVFN_SDIO PCI_DEVFN(SDIO_DEV,SDIO_FUNC)
/* SD Port */ #define SD_DEV 0x12 #define SD_FUNC 0 -# define SD_DEV_FUNC PCI_DEVFN(SD_DEV,SD_FUNC) +# define SOC_DEVFN_SD PCI_DEVFN(SD_DEV,SD_FUNC)
/* SATA */ #define SATA_DEV 0x13 #define SATA_FUNC 0 -# define SATA_DEV_FUNC PCI_DEVFN(SATA_DEV,SATA_FUNC) - +# define SOC_DEVFN_SATA PCI_DEVFN(SATA_DEV,SATA_FUNC)
/* xHCI */ #define XHCI_DEV 0x14 @@ -67,22 +66,22 @@ # define XHCI_FUS_REG 0xE0 # define XHCI_FUNC_DISABLE (1 << 0) # define XHCI_USB2PR_REG 0xD0 -# define XHCI_DEV_FUNC PCI_DEVFN(XHCI_DEV,XHCI_FUNC) +# define SOC_DEVFN_XHCI PCI_DEVFN(XHCI_DEV,XHCI_FUNC)
/* LPE Audio */ #define LPE_DEV 0x15 #define LPE_FUNC 0 -# define LPE_DEV_FUNC PCI_DEVFN(LPE_DEV,LPE_FUNC) +# define SOC_DEVFN_LPE PCI_DEVFN(LPE_DEV,LPE_FUNC)
/* OTG */ #define OTG_DEV 0x16 #define OTG_FUNC 0 -# define OTG_DEV_FUNC PCI_DEVFN(LPE_DEV,LPE_FUNC) +# define SOC_DEVFN_OTG PCI_DEVFN(LPE_DEV,LPE_FUNC)
/* MMC Port */ #define MMC45_DEV 0x17 #define MMC45_FUNC 0 -# define MMC45_DEV_FUNC PCI_DEVFN(MMC45_DEV,MMC45_FUNC) +# define SOC_DEVFN_MMC45 PCI_DEVFN(MMC45_DEV,MMC45_FUNC)
/* Serial IO 1 */ #define SIO1_DEV 0x18 @@ -102,24 +101,24 @@ # define I2C6_FUNC 6 # define I2C7_DEV SIO1_DEV # define I2C7_FUNC 7 -# define SIO_DMA1_DEV_FUNC PCI_DEVFN(SIO_DMA1_DEV,SIO_DMA1_FUNC) -# define I2C1_DEV_FUNC PCI_DEVFN(I2C1_DEV,I2C1_FUNC) -# define I2C2_DEV_FUNC PCI_DEVFN(I2C2_DEV,I2C2_FUNC) -# define I2C3_DEV_FUNC PCI_DEVFN(I2C3_DEV,I2C3_FUNC) -# define I2C4_DEV_FUNC PCI_DEVFN(I2C4_DEV,I2C4_FUNC) -# define I2C5_DEV_FUNC PCI_DEVFN(I2C5_DEV,I2C5_FUNC) -# define I2C6_DEV_FUNC PCI_DEVFN(I2C6_DEV,I2C6_FUNC) -# define I2C7_DEV_FUNC PCI_DEVFN(I2C7_DEV,I2C7_FUNC) +# define SOC_DEVFN_SIO_DMA1 PCI_DEVFN(SIO_DMA1_DEV,SIO_DMA1_FUNC) +# define SOC_DEVFN_I2C1 PCI_DEVFN(I2C1_DEV,I2C1_FUNC) +# define SOC_DEVFN_I2C2 PCI_DEVFN(I2C2_DEV,I2C2_FUNC) +# define SOC_DEVFN_I2C3 PCI_DEVFN(I2C3_DEV,I2C3_FUNC) +# define SOC_DEVFN_I2C4 PCI_DEVFN(I2C4_DEV,I2C4_FUNC) +# define SOC_DEVFN_I2C5 PCI_DEVFN(I2C5_DEV,I2C5_FUNC) +# define SOC_DEVFN_I2C6 PCI_DEVFN(I2C6_DEV,I2C6_FUNC) +# define SOC_DEVFN_I2C7 PCI_DEVFN(I2C7_DEV,I2C7_FUNC)
/* Trusted Execution Engine */ #define TXE_DEV 0x1a #define TXE_FUNC 0 -# define TXE_DEV_FUNC PCI_DEVFN(TXE_DEV,TXE_FUNC) +# define SOC_DEVFN_TXE PCI_DEVFN(TXE_DEV,TXE_FUNC)
/* HD Audio */ #define HDA_DEV 0x1b #define HDA_FUNC 0 -# define HDA_DEV_FUNC PCI_DEVFN(HDA_DEV,HDA_FUNC) +# define SOC_DEVFN_HDA PCI_DEVFN(HDA_DEV,HDA_FUNC)
/* PCIe Ports */ #define PCIE_DEV 0x1c @@ -131,15 +130,15 @@ # define PCIE_PORT3_FUNC 2 # define PCIE_PORT4_DEV PCIE_DEV # define PCIE_PORT4_FUNC 3 -# define PCIE_PORT1_DEV_FUNC PCI_DEVFN(PCIE_DEV,PCIE_PORT1_FUNC) -# define PCIE_PORT2_DEV_FUNC PCI_DEVFN(PCIE_DEV,PCIE_PORT2_FUNC) -# define PCIE_PORT3_DEV_FUNC PCI_DEVFN(PCIE_DEV,PCIE_PORT3_FUNC) -# define PCIE_PORT4_DEV_FUNC PCI_DEVFN(PCIE_DEV,PCIE_PORT4_FUNC) +# define SOC_DEVFN_PCIE_PORT1 PCI_DEVFN(PCIE_DEV,PCIE_PORT1_FUNC) +# define SOC_DEVFN_PCIE_PORT2 PCI_DEVFN(PCIE_DEV,PCIE_PORT2_FUNC) +# define SOC_DEVFN_PCIE_PORT3 PCI_DEVFN(PCIE_DEV,PCIE_PORT3_FUNC) +# define SOC_DEVFN_PCIE_PORT4 PCI_DEVFN(PCIE_DEV,PCIE_PORT4_FUNC)
/* EHCI */ #define EHCI_DEV 0x1d #define EHCI_FUNC 0 -# define EHCI_DEV_FUNC PCI_DEVFN(EHCI_DEV,EHCI_FUNC) +# define SOC_DEVFN_EHCI PCI_DEVFN(EHCI_DEV,EHCI_FUNC)
/* Serial IO 2 */ #define SIO2_DEV 0x1e @@ -155,23 +154,24 @@ # define HSUART2_FUNC 4 # define SPI_DEV SIO2_DEV # define SPI_FUNC 5 -# define SIO_DMA2_DEV_FUNC PCI_DEVFN(SIO_DMA2_DEV,SIO_DMA2_FUNC) -# define PWM1_DEV_FUNC PCI_DEVFN(PWM1_DEV,PWM1_FUNC) -# define PWM2_DEV_FUNC PCI_DEVFN(PWM2_DEV,PWM2_FUNC) -# define HSUART1_DEV_FUNC PCI_DEVFN(HSUART1_DEV,HSUART1_FUNC) -# define HSUART2_DEV_FUNC PCI_DEVFN(HSUART2_DEV,HSUART2_FUNC) -# define SPI_DEV_FUNC PCI_DEVFN(SPI_DEV,SPI_FUNC) +# define SOC_DEVFN_SIO_DMA2 PCI_DEVFN(SIO_DMA2_DEV,SIO_DMA2_FUNC) +# define SOC_DEVFN_PWM1 PCI_DEVFN(PWM1_DEV,PWM1_FUNC) +# define SOC_DEVFN_PWM2 PCI_DEVFN(PWM2_DEV,PWM2_FUNC) +# define SOC_DEVFN_HSUART1 PCI_DEVFN(HSUART1_DEV,HSUART1_FUNC) +# define SOC_DEVFN_HSUART2 PCI_DEVFN(HSUART2_DEV,HSUART2_FUNC) +# define SOC_DEVFN_SPI PCI_DEVFN(SPI_DEV,SPI_FUNC)
/* Platform Controller Unit */ #define PCU_DEV 0x1f # define LPC_DEV PCU_DEV # define LPC_FUNC 0 +# define PCH_DEVFN_LPC PCI_DEVFN(LPC_DEV,LPC_FUNC) +# define LPC_BDF PCI_DEV(0, LPC_DEV, LPC_FUNC) + # define SMBUS_DEV PCU_DEV # define SMBUS_FUNC 3 -# define LPC_DEV_FUNC PCI_DEVFN(LPC_DEV,LPC_FUNC) -# define LPC_BDF PCI_DEV(0, LPC_DEV, LPC_FUNC) -# define SMBUS_DEV_FUNC PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC) +# define SOC_DEVFN_SMBUS PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC)
#define SOC_DEVID 0x0f00 #define GFX_DEVID 0x0f31
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