Change in coreboot[master]: soc/intel/common/block: [WIP]Add Intel common FAST_SPI code

[Barnali Sarkar (Code Review)]

Barnali Sarkar has posted comments on this change. ( https://review.coreboot.org/18557 )

Change subject: soc/intel/common/block: [WIP]Add Intel common FAST_SPI code
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Patch Set 14:

(1 comment)

https://review.coreboot.org/#/c/18557/14/src/soc/intel/common/block/include/...
File src/soc/intel/common/block/include/intelblocks/fast_spi.h:

Line 157: void enable_spibar(uintptr_t spi_base_address, device_t dev);
> Why is get_fast_spi_bar() and fast_spi_flash_ctlr_reg_read() there? If you

Okay, will check and fix these functions.
> > > > >

the other piece missing to this fast spi is the actually spi_flash interface. This is only providing one half of what is required when one is assuming fast spi is the boot medium.
> > > > >

I think you meant the flash_controller part of it.
Right now, we have pushed the bootblock part of it. The Romstage flash_controller part implementation has been already started which will require these definitions of SPI PCI config space offset and MMIO Space offset. We will push that next.